• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.3
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• pp.39-52
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• 2009

Scale Invariant Feature Transform (SIFT) is an effective algorithm in object recognition, panorama stitching, and image matching, however, due to its complexity, real time processing is difficult to achieve with software approaches. This paper proposes using a reconfigurable hardware processor with integer half kernel. The integer half kernel Gaussian reduces the Gaussian pyramid complexity in about half [] and the reconfigurable processor carries out a parallel implementation of a full search Fast SIFT algorithm. We use a low memory, fine grain single instruction stream multiple data stream (SIMD) pixel processor that is currently being developed. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and I/O capabilities of the processor which results in a system that can perform real time image and video compression. We apply this novel implementation to images and measure the effectiveness. Experimental simulation results indicate that the proposed implementation is capable of real time applications.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.2
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• pp.100-107
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• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements(PEs) and operates on a 3-stage pipelining. Experimental results for the JPEG encoding algorithm indicate that the proposed parallel processor outperforms conventional parallel processors in terms of performance and energy efficiency. In addition, the proposed parallel processor architecture was developed and verified with verilog HDL and a FPGA prototype system.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.1
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• pp.117-123
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• 2012

This paper implements mobile Worldwide Interoperability for Microwave Access (WiMAX) receiver using Software Defined Radio (SDR) technology. SDR system is difficult to implement on the mobile handset because of restrictions that are computing power and under space constraints. The implemented receiver processes mobile WiMAX software modem on Open Multimedia Application Platform (OMAP) System on Chip (SoC) and Field Programmable Gate Array (FPGA). OMAP SoC is composed of ARM processor and Digital Signal Processor (DSP). ARM processor supports Single Instruction Multiple Data (SIMD) instruction which could operate on a vector of data with a single instruction and DSP is powerful image and video accelerators. For this reason, we suggest the possibility of SDR technology in the mobile handset. In order to verify the performance of the mobile WiMAX receiver, we measure the software modem runtime respectively. The experimental results show that the proposed receiver is able to do real-time signal processing.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.18-20
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• 2011

최근 컴퓨터 비전의 활용 영역이 증가함에 따라 컴퓨터 비전의 대표적인 라이브러리인 openCV의 사용 또한 증가하는 추세이다. openCV 에는 컴퓨터 비전 알고리즘의 특성상 massive 한 연산을 수행해야 하는 부분이 상당수 존재한다. 본 논문은 이러한 연산량의 부담을 줄임으로써 openCV 의 성능 향상을 위한 아키텍처를 연구한다. openCV 의 massive 한 연산은 라이브러리 함수에 있는 내부 반복문에서 발생하기 때문에, 본 논문은 반복문의 특성을 분석하고 이를 가속할 수 있는 아키텍처가 무엇인지 연구한다. 결론적으로 반복문의 각 iteration 이 독립적일 경우에는 SIMD (Single Instruction Multiple Data)와 SIMT (Single Instruction Multiple Thread)이 적합하며 반복문의 각 iteration 이 의존적일 경우에는 MIMD (Multiple Instruction Multiple Data)를 바탕으로 하는 파이프라인 아키텍처가 적합하다.

• The Journal of the Korea Contents Association
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• v.12 no.1
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• pp.30-37
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• 2012

A memory system with the linear skewing scheme has been regarded as one of suitable memory systems for a single instruction, multiple data (SIMD) architecture. The memory system supports simultaneous access n data to m memory modules within various access types with a constant interval in an arbitrary position in two dimensional data array of $M{\times}N$. Although $m{\times}cells$ memory cells are physically required to support logical two dimensional $M{\times}N$ array of data by means of the memory system, at least (m-n)${\times}cells$ memory cells remain in disuse, where cells is (M-1)/q+(N-1)/$p{\times}{\lceil}M/q{\rceil}+1$. On keeping functionalities the memory system supports, $(n{\times}t){\times}N/p$ out of a number of unused memory cells, where t>0, being used as local buffer memories for n processing elements is proposed in this paper.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.129-132
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• 2002

AE64000 is the 64-bit high-performance microprocessor that ADC Co. Ltd. is developing for an embedded environment. It has a 5-stage pipeline and uses Havard architecture with a separated instruction and data caches. It also provides SIMD-like DSP and FP operation by enabling the 8/16/32/64-bit MAC operation on 64-bit registers. AE64000 processor implements the EISC ISA and uses the instruction folding mechanism (Instruction Folding Unit) that effectively deals with LERI instruction in EISC ISA. But this unit makes branch prediction behavior difficult. In this paper, we designs a branch predictor optimized for AE64000 Pipeline and develops a AES4000 simulator that has cycle-level precision to validate the performance of the designed branch predictor. We makes TAC(Target address cache) and BPT(branch prediction table) seperated for effective branch prediction and uses the BPT(removed indexed) that has no address tags.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.27 no.3
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• pp.413-426
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• 2017

In this paper, we propose an adder that can be applied to data encrypted with a fully homomorphic encryption scheme and an addition method with improved performance that can be applied when adding multiple data. The proposed arithmetic adder is based on the Kogge-Stone Adder method with the optimal circuit level among the existing hardware-based arithmetic adders and suitable to apply the cryptographic SIMD (Single Instruction for Multiple Data) function on encrypted data. The proposed multiple addition method does not add a large number of data by repeatedly using Kogge-Stone Adder which guarantees perfect addition result. Instead, when three or more numbers are to be added, three numbers are added to C (Carry-out) and S (Sum) using the full-adder circuit implementation. Adding with Kogge-Stone Adder is only when two numbers are finally left to be added. The performance of the proposed method improves dramatically as the number of data increases.

• ETRI Journal
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• v.30 no.4
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• pp.576-586
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• 2008

In most parallel loops of embedded applications, every iteration executes the exact same sequence of instructions while manipulating different data. This fact motivates a new compiler-hardware orchestrated execution framework in which all parallel threads share one fetch unit and one decode unit but have their own execution, memory, and write-back units. This resource sharing enables parallel threads to execute in lockstep with minimal hardware extension and compiler support. Our proposed architecture, called multithreaded lockstep execution processor (MLEP), is a compromise between the single-instruction multiple-data (SIMD) and symmetric multithreading/chip multiprocessor (SMT/CMP) solutions. The proposed approach is more favorable than a typical SIMD execution in terms of degree of parallelism, range of applicability, and code generation, and can save more power and chip area than the SMT/CMP approach without significant performance degradation. For the architecture verification, we extend a commercial 32-bit embedded core AE32000C and synthesize it on Xilinx FPGA. Compared to the original architecture, our approach is 13.5% faster with a 2-way MLEP and 33.7% faster with a 4-way MLEP in EEMBC benchmarks which are automatically parallelized by the Intel compiler.

• Journal of the Korea Society of Computer and Information
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• v.16 no.5
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• pp.1-11
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• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements (PEs) and operates on a 3-stage pipelining. Experimental results indicated that the proposed parallel processor outperforms conventional parallel processors in terms of performance. In addition, our proposed parallel processor outperforms commercial high-performance TI C6416 DSP in terms of performance (1.4-31.4x better) and energy efficiency (5.9-8.1x better) with same 130nm technology and 720 clock frequency. The proposed parallel processor was developed with verilog HDL and verified with a FPGA prototype system.

• Spatial Information Research
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• v.17 no.3
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• pp.371-379
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• 2009

Recently, GPU (Graphics Processing Unit) has been improved rapidly on the need of speed for gaming. As a result, GPU contains multiple ALU (Arithmetic Logic Unit) for parallel processing of a lot of graphics data, such as transform, ray tracing, etc. Therefore, this paper proposed a technique for parallel processing of spatial data using GPU. Spatial data consists of multiple coordinates, and each coordinate contains value of x and y axis. To display spatial data graphics operations have to be processed to large amount of coordinates. Because the graphics operation is identical and coordinates are multiple data, SIMD (Single Instruction Multiple Data) parallel processing of GPU can be used for processing of spatial data to improve performance. This paper implemented SIMD parallel processing of spatial data using two kinds of SDK (Software Development Kit). CUDA and ATI Stream are used for NVIDIA and ATI GPU respectively. Experiments that measure time of calculation for graphics operations are carried out to observe enhancement of performance. Experimental result is reported that proposed method can enhance performance up to 1,162% for graphics operations. The proposed method that uses parallel processing with GPU for spatial data can be generally used to enhance performance for applications which deal with large amount of spatial data.