• Proceedings of the Korean Information Science Society Conference
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• 2011.06b
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• pp.313-316
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• 2011

SRAM-based FPGAs are very sensitive to single event upset(SEU) induced by space irradiation. To mitigate SEU effects, space applications employ some mitigation schemes. The triple modular redundancy(TMR) is a well-known mitigation scheme. It uses one or three voters as well as three identical blocks performing the same work. The voters can mask out one error in the outputs from the three replicated blocks. One SEU error in TMRed circuits can be masked but it needs to be detected for some reasons such as to analyze the SEU effects in the satellite or to recover the circuits from the error before additional error occur. In this paper, we developed a fault detection circuit and reporting system to detect a fault on the TMRed circuits. To verify our error detection circuit and reporting circuit, we performed an irradiation test at MC-50 Cyclotron. Experimental results showed that error detection circuit can detect a fault on the TMRed test circuit in radiation environment.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.8
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• pp.1440-1446
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• 2008

In this paper, a novel TMR (Triple Modular Redundancy) memory structure is proposed using state feedback control of asynchronous sequential machines. The main ability of the proposed structure is to correct the fault of SEU (Single Event Upset) asynchronously without resorting to the global synchronous clock. A state-feedback controller is combined with the TMR realized as a closed-loop asynchronous machine and corrective behavior is operated whenever an unauthorized state transition is observed so as to recover the failed state of the asynchronous machine to the original one. As a case study, an asynchronous machine modelling of TMR and the detailed procedure of controller construction are presented. A simulation results using VHDL shows the validity of the proposed scheme.

• Nuclear Engineering and Technology
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• v.49 no.8
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• pp.1589-1599
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• 2017

Field programmable gate arrays (FPGAs) are getting more attention in safety-related and safety-critical application development of nuclear power plant instrumentation and control systems. The high logic density and advancements in architectural features make static random access memory (SRAM)-based FPGAs suitable for complex design implementations. Devices deployed in the nuclear environment face radiation particle strike that causes transient and permanent failures. The major reasons for failures are total ionization dose effects, displacement damage dose effects, and single event effects. Different from the case of space applications, soft errors are the major concern in terrestrial applications. In this article, a review of radiation effects on FPGAs is presented, especially soft errors in SRAM-based FPGAs. Single event upset (SEU) shows a high probability of error in the dependable application development in FPGAs. This survey covers the main sources of radiation and its effects on FPGAs, with emphasis on SEUs as well as on the measurement of radiation upset sensitivity and irradiation experimental results at various facilities. This article also presents a comparison between the major SEU mitigation techniques in the configuration memory and user logics of SRAM-based FPGAs.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.4
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• pp.35-41
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• 2008

When memory devices are exposed to a space environment. they suffer various effects such as SEU(Single Event Upset). For these reasons, memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, the error detection and correction strategy in the Mass Memory Unit(MMU) of the STSAT-3 is discussed. The probability equation of un-recoverable SEUs in the mass memory system is derived when the whole memory is encoded and decoded by the RS(10,8) Reed-Solomon code. Also the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. The analyzed results can be used to determine the period of scrubbing the whole memory, which is one of the important parameters in the design of the MMU.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.1
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• pp.97-101
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• 2024

In this paper, we present the implementation of proton beam irradiation test logic and test results for Xilinx's RFSoC FPGA. In addition to the FPGA function, RFSoC is a chip that integrates CPU, ADC, and DAC and is attracting attention in the defense and space industries aimed at reducing the size of the chip. In order to use these chips in a space environment, an analysis of radiation effects was required and radiation mitigation measures were required. Through the proton irradiation test, the logic to measure the radiation effect of RFSoC was designed. Logic for comparing values stored in memory with normal values was implemented, and protons were irradiated to RFSoC to measure SEU generated in the block memory area. To alleviate the occurrence of SEU in other areas, TMR and SEM were applied and designed. Through the test results, we intend to verify this test configuration and establish an environment in which logic design for satellites can be verified in the future.

• International Journal of Aeronautical and Space Sciences
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• v.3 no.2
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• pp.31-39
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• 2002

In this paper, KOMPSAT-2 on-board fault and ground recovery management design is addressesed in terms of hardware and software components which provide failure detection and spacecraft safing for anomalies which threaten spacecraft survival. It also includes ground real time up-commanding operation to recover the system safely. KOMPSAT-2 spacecraft fault and recovery management is designed such that the subsequent system configuration due to system initialization is initiated and controlled by processors. This paper will show that KOMPSAT-2 has a new design feature of CPU SEU mitigation for the possible upsets in the processor CPUs as a part of on-board fault management design. Recovery management of processor switching has two different ways: gang switching and individual switching. This paper will show that the difficulties of using multiple-processor system can be managed by proper design implementation and flight operation.