• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1368-1370
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• 2005

Satellite is operated only with internal battery when separated from rocket. Internal battery is charged only from SAR(solar Array Regulator), solar cell. So battery will be exhausted and purpose of satellite will be failed if load module is out of order or short. This paper proposed real time current limiter which operated by telemetry of outer processor. This current limiter operates by control signal simultaneously cuts off over current by self over current sensing circuit. So it can reduce waste of battery energy and over load of outer processor.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.51-54
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• 1998

In this paper, we describe the design of the ATM Mux/Demux circuit between BSC and MSC for IMT-2000 Network. This ATM Mux/Demux circuit culd support 155Mbps optic interface with MSC. Using the CAM and DPRAM, this circuit performs ATM cell Mux/Demux functions in the BSC. MPC 860SAR processor was used for the signaling with MSC in this design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1C
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• pp.46-54
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• 2006

The design method of synthetic aperture radar processor (SARP) in the critical design stage is to describe the processing algorithm, to estimate the fractional errors, and to set out the software (SW) and hardware (HW) mapping. The previous design methods for SARP are complex and depend on HW. Therefore, this paper proposes a critical design method that is of more general and independent of HW. This methodology can be applied for developing the space-based SARP using range-Doppler algorithm (RDA).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.369-378
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• 2003

This paper presents design and VLSI implementations of a reassembly processor for ATM/AAL. The assembly processor is responsible for processing ATM cells from the receive physical interface. It controls the transfer of the AAL payload to host memory and performs all necessary SAR and CPCS checks. We propose the improved structure of cell identification algorithm and smart scatter method for host memory management. The proposed cell identification algorithm quickly locates the appropriate reassembly VC table based on the received VPI./VCI channel value in the ATM header. The cell identification algorithm also allow complete freedom in assignment of VCI/VPI values. The reassembly processor uses a smart scatter method to write cell payload data to host memory. It maintains the scatter operation and controls the incoming DMA block during scatter DMA to host memory. The proposed reassembly processor can perform reassembly checks on AAL. OAM cell. For an AAL5 connection, only CPCS checks, including the CRC32, are performed. In this paper, we proposed a practical reassembly architecture. The design of reassembly processor has become feasible using 0.6${\mu}{\textrm}{m}$ CMOS gate array technology.

• Journal of Space Technology and Applications
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• v.1 no.1
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• pp.33-40
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• 2021

Based on the requirements of a total weight of 42 kg or less, the NEXTSat-2 SAR (synthetic aperture radar) system was developed. As the NEXTSat-2 is a small-sized satellite, the SAR system was designed to account for about 40% of the dry mass of the payload relative to the total mass. Among the major components of the SAR system - which are an antenna, an RF transceiver, a baseband signal processor, and a power unit - a part with a particularly large dry mass is the antenna, the core of the SAR system. Whereas various selections are possible in consideration of gain and efficiency when designing the antenna, the micro-strip patch array antenna was adopted by reflecting the dry mass, power, and resolution required by the NEXTSat-2 project. In order to meet the mission requirement of the NEXTSat-2, the antenna was developed with a frequency of 9.65 GHz, a gain of 42.7 dBi, and a return loss of -15 dB. The performance of the antenna was verified by conducting a field test onboard the vehicle.

• Journal of IKEEE
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• v.24 no.3
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• pp.797-802
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• 2020

In this paper, we presents the design and implementation results of the FFT processor, which supports 4096 points of operation with less memory by sharing several memory used in the base-4 systolic array FFT processor into one memory. Sharing memory provides the advantage of reducing the area, and also simplifies the flow of data as I/O of the data progresses in one memory. The presented FFT processor was implemented and verified on the FPGA device. The implementation resulted in 51,855 CLB LUTs, 29,712 CLB registers, 8 block RAM tiles and 450 DSPs, and confirmed that the memory area could be reduced by 65% compared to the existing base-4 systolic array structure.

• Current Industrial and Technological Trends in Aerospace
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• v.8 no.2
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• pp.98-104
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• 2010

The demand for Satellite Images is continuously increasing owing to the various applications of optical satellite images. However, the acquisition of optical images has a limitation due to problems of weather and day & night. because an optical satellite makes images with reflections of sunlight. Therefore, SAR Satellite, which uses electromagnetic waves to make an image, gives increased demand to various applications. It also makes increased interest. In this paper, a calibration and validation system, which is an essential element for high quality Radar images, is studied.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.11a
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• pp.255-258
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• 2004

The SAR(Solar Array Regulator) of KOMPSAT(Korea Multi Purpose SATellite)-1, 2 regulates a photovoltaic power according to the duty ratio commands of the ECU. But the ECU has so many other jobs that it can not calculate the solar array condition immediately. It means the SAR cannot always generate the maximum power of a photovoltaic. Nowadays, the commercial photovoltaic systems are using a controller operated by digital processing. But the usage for satellite is not adaptable. It is not easy to find the processor of the space grade and the price is expensive. So in this paper, the simple analog MPPT(Maximum Power Point Tracking) algorithm is proposed for the small satellite in LEO. This algorithm does not need any calculation of power by multiplication of voltage and current md a measurement of the solar array temperature. It is consist of only two sample and hold circuits, two comparators, a flip-flop, and an integrator. The proposed MPPT algorithm is verified by the simulation and experimental.

• Korean Journal of Remote Sensing
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• v.26 no.3
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• pp.335-346
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• 2010

Recently, ESA (European Space Agency) has launched CryoSAT-2 for polar ice observations. CryoSAT-2 is equipped with a SIRAL (SAR/interferometric radar altimeter), which is a high spatial resolution radar altimeter. Conventional altimeters cannot measure a precise three-dimensional ground position because of the large footprint diameter, while SIRAL altimeter system accomplishes a precise three-dimensional ground positioning by means of interferometric synthetic aperture radar technique. In this study, we developed an efficient SIRAL SARIn mode processing technique to measure a precise three-dimensional ground position. We first simulated SIRAL SARIn RAW data for the ideal target by assuming the flat Earth and linear flight track, and second accessed the precision of three-dimensional geopositioning achieved by the proposed algorithm. The proposed algorithm consists of 1) azimuth processing that determines the squint angle from Doppler centroid, and 2) range processing that estimates the look angle from interferometric phase. In the ideal case, the precisions of look and squint angles achieved by the proposed algorithm were about -2.0 ${\mu}deg$ and 98.0 ${\mu}deg$, respectively, and the three-dimensional geopositioning accuracy was about 1.23 m, -0.02 m, and -0.30 m in X, Y and Z directions, respectively. This means that the SIRAL SARIn mode processing technique enables to measure the three-dimensional ground position with the precision of several meters.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.287-290
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• 2002

This paper rotates to tile FPGA that is reffered to as the UTOSPI. The design goal of the FPGA is to convert the UTOPIA-3 bus interface to the SPI-3 bus interface, so that the SAR chips on the ATM interface board can be interfaced to the packet processor through this FPGA. We Propose a new architecture that has two Dual Port RAMs and flow control signals. To buffer data, the UTOSPI has a Dual port RAM in the receive direction and the same size of that in the transmit direction. This design has been implemented, compiled, and tested using a Xilinx Virtex-I XCV-300E FPGA.