• Proceedings of the KAIS Fall Conference
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• 2009.12a
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• pp.511-514
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• 2009

현재 일반적으로 사용되는 300cc 소형엔진 기화기의 최적화 및 성능 향상을 위하여 유동해석을 수행하였다. 베르누이의 정리를 기본으로, 성능을 발휘하는 주요 설계인자인 기화기 내부의 벤튜리 튜브의 각도, 길이 등을 변수로 하여 유동해석을 수행하였다. 그 결과를 분석하여 최적화된 모델을 제시하였다. 결론적으로, 유동 해석을 바탕으로 기존 사양 대비 향상된 성능의 모델을 제시하였다. 유동해석을 통해 기화기 내부의 벤튜리관에 곡면(Rounding)처리를 적용함으로 기화기에서 소모되는 흡기저항을 줄여 펌핑로스를 저감활수 있음을 확인하였다. 펌핑로스의 저감은 엔진 연비의 향상과 엔진토크에 긍정적 효과로 작용할 것으로 기대된다. 벤튜리관의 출구 각도를 감소시킴으로 박리를 개선하여 Dead Volume을 줄임으로서 기존 모델에 대비하여 원활해진 유동의 흐름을 얻을 수 있었다. 이는 흡기유량을 증대시키고 엔진출력을 상승시키는 효과로 작용할 것으로 예상된다.

• 한국신재생에너지학회:학술대회논문집
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• 2006.11a
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• pp.320-323
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• 2006

A numerical study is made of a manifold and bipolar plate in polymer electrolyte fuel cells, the aim of the present study is to describe the characteristics of flow pattern In manifold and bipolar plate. The present work shows that the flow pattern in the bipolar plate is affected by the penetration flow through GDL characterized by clamping pressure and GDL intrusion in to a channel area. Manifold geometry also affects the flow distribution. The recirculation flow by bent duct destroy even distribution In manifold, the present work shows that corner rounding can improve the manifold performance.

• Journal of the korean Society of Automotive Engineers
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• v.6 no.3
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• pp.45-54
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• 1984

Bending strength of an internal gear tooth is discussed as tooth form factor taking into account the actual stress magnitude. Stress analysis was carried out by the finite element method(FEM) for the calculation of tooth form factor of an internal gear. This paper also investigated the influences of number of teeth and addendum modification coefficient of the internal gear and the influences of number of teeth, addendum modification coefficient, pressure angle, radius of rounding of tooth tip, and bottom clearance coefficient of the pinion-shaped cutter on tooth form factor of internal gear. Generalizing the resultant data, a simple formula for the tooth form factor of an internal gear was derived for the calculation of tooth bending strength of an internal gear.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.778-780
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• 1999

Arithmetic unit speed depends strongly on the algorithms employed to realize the basic arithmetic operations.(add, subtract multiply, and divide) and on the logic design. Recent advances in VLSI have increased the feasibility of hardware implementation of floating point arithmetic units and microprocessors require a powerful floating-point processing unit as a standard option. This paper describes the design of floating-point multiplier for IEEE 754-1985 Single-Precision operation. Booth encoding algorithm method to reduce partial products and a Wallace tree of 4-2 CSA is adopted in fraction multiplication part to generate the $32{\times}32$ single-precision product. New scheme of rounding and sticky-bit generation is adopted to reduce area and timing. Also there is a true sign generator in this design. This multiplier have been implemented in a ALTERA FLEX EPF10K70RC240-4.

• Proceedings of the KSR Conference
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• 2004.06a
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• pp.1096-1101
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• 2004

Generally, the buckling of thin-walled structures has studied for rectangular sections or circular sections. Rectangular sections have small stiffness and circular sections have large stiffness when they are compared with rectangular sections for local buckling. But both of them have similar stiffness to column buckling. Therefore in this paper, we are going to analyze the local buckling for the box section with rounded comer and compare with rectangular section. Also we confirm that the rounded comer section has larger local buckling strength than rectangular section.

• Communications for Statistical Applications and Methods
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• v.8 no.3
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• pp.719-729
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• 2001

Overlap Maximization is a sampling technique to reduce survey costs and costs associated with the survey. It was first studied by Keyfitz(1951). Ernst(1998) presented a remarkable procedure for maximizing the overlap when the sampling units can be selected for two identical stratified designs simultaneously, But the approach involves mimicking the behaviour of nonlinear function by linear function and so it is less direct, even though the stratification problem for the overlap corresponds directly to the linear programming problem. furthermore, it uses the controlled selection algorithm that repeatedly needs zero-restricted controlled roundings, which are solutions of capacitated transportation problems. In this paper we suggest a comparatively simple procedure to use linear programming in order to maximize the overlap. We show how this procedure can be implemented practically.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.11
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• pp.915-922
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• 1991

This research paper presents an ALU unit using 1.0$\mu$m CMOS technology capable of doing IEEE standard single and double precision floating poing calculation within 32ns (2 clock) at 60 MHz clock speed. This 32ns speed was achieved by using 9ns 1's complement arithmetic 54 bit carry select adder instead of previous 2's complement adders. On the first cycle, this adder is used for addition or subtraction and the second cycle uses this adder for rounding. This reduces the number of required adders from two to one. Speed improvement is 2 to 5 times compared with previous 40MHz design. Design goal was 60MHz, however, this unit is functioning at 80 MHz at room temperature.

• Proceedings of the Korea Concrete Institute Conference
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• 1999.04a
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• pp.727-732
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• 1999

In this research, we made an experiment on the 10 specimen beams that we made. The specimen beams consist of 4 steel plate strengthening beams and 5 carbon fiber sheet strengthening beams. We applied the methods of notch, rounding off a edge, anchor bolt and side shear strengening to the steel plate and for the case of carbon fiber sheet, we applied the methods of anchor bolt, line anchor and shear strengthening. After all the cases were applied, the beams was measured and analyzed about the behavior property of strengthened beams, th ability of strengthening method, the relation between load and the shape of failure, the crack load, the yield load, the shape of crack pattern, the increasing rate from yield load and maximum load and the strain of rebar. All the strengthening methods resulted in almost same value until the yield load, and it wasn't quite different from the theoretical value. In comparison with existing method, the SER, SEAS for the steel plate and the CEA, CESS, CCESS for carbon fiber sheet showed the increasement of ductility with big displacement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1332-1344
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• 1996

This paper presents a pipelined floating point multiplier(FMUL) for superscalar microprocessors that conbines radix-16 recoding scheme based on signed-digit(SD) number system and new rouding and normalization scheme. The new rounding and normalization scheme enable the FMUL to compute sticky bit in parallel with multiple operation and elminate timing delay due to post-normalization. By expoliting SD radix-16 recoding scheme, we can achieves further reduction of silicon area and computation time. The FMUL can execute signle-precision or double-precision floating-point multiply operation through three-stage pipelined datapath and support IEEE standard 754. The algorithm andstructure of the designed multiplier have been successfully verified through Verilog HOL modeling and simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1345-1359
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• 1996

This paper presents a floating point arithmetic unit (FPAU) for supescalar microprocessor that executes fifteen operations such as addition, subtraction, data format converting, and compare operation using two pipelined arithmetic paths and new rounding and normalization scheme. By using two pipelined arithmetic paths, each aritchmetic operation can be assigned into appropriate arithmetic path which high speed operation is possible. The proposed normalization an rouding scheme enables the FPAU to execute roundig operation in parallel with normalization and to reduce timing delay of post-normalization. And by predicting leading one position of results using input operands, leading one detection(LOD) operation to normalize results in the conventional arithmetic unit can be eliminated. Because the FPAU can execuate fifteen single-precision or double-precision floating-point arithmetic operations through three-stage pipelined datapath and support IEEE standard 754, it has appropriate structure which can be ingegrated into superscalar microprocessor.