• Journal of Korea Multimedia Society
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• v.6 no.3
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• pp.419-428
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• 2003

Several methods have been studied to prune the parasitic branches that cause unfortunately from thinning a shape to get its skeleton. We found that the symmetric path finding method was most efficient because it followed the boundary pixels of the shape just once. In this paper, its extended method is proposed to apply to removing the noise branches that protrude out of the boundary of a segmented or extracted shape in a given image. The proposed method can remove a noise branch with one-pixel width and also remove the noise branch that includes a round shape called a noise blob. The method uses a 4-8-directional boundary-following technique to determine symmetric paths and finds noise branches with noise blobs by detecting quasi-symmetric paths. Its time complexity is a linear function of the number of boundary pixels. Interactively selectable parameters are used to define various types of noise branches flexibly, which are the branch - size parameter and the blob-size parameter. Experimental results for a practical shape and various artificial shapes showed that the proposed method was very useful for simplifying the shapes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2517-2524
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• 2012

This paper describes an efficient implementation of KS(Korea Standards) block cipher algorithm ARIA. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit and four modes of operation including ECB, CBC, OFB and CTR. A hardware sharing technique, which shares round function in encryption/decryption with key initialization, is employed to reduce hardware complexity. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a $0.13-{\mu}m$ CMOS cell library. It has 46,100 gates on an area of $684-{\mu}m{\times}684-{\mu}m$ and the estimated throughput is about 1.28 Gbps at 200 MHz@1.2V.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.207-213
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• 2019

Recently, the importance for internet of things (IoT) security has increased enormously and hardware-based compact chips are needed in IoT communication industries. In this paper, we propose low-complexity crypto-processor that unifies advanced encryption standard (AES), academy, research, institute, agency (ARIA), and CLEFIA protocols into one combined design. In the proposed crypto-processor, encryption and decryption processes are shared, and 128-bit round key generation process is combined. Moreover, the shared design has been minimized to be adapted in generic IoT devices and systems including lightweight IoT devices. The proposed crypto-processor was implemented in Verilog hardware description language (HDL) and synthesized to gate level circuit in 65nm CMOS process, which results in 11,080 gate counts. This demonstrates roughly 42% better than the aggregates of three algorithm implementations in the aspect of gate counts.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.5
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• pp.25-34
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• 2009

Many conference systems over the Internet require authenticated group key agreement (AGKA) for secure and reliable communication. After Shamir [1] proposed the ID-based cryptosystem in 1984, ID-based AGKA protocols have been actively studied because of the simple public key management. In 2006, Zhou et al. [12] proposed two-round ID-based AGKA protocol which is very efficient in communication and computation complexity. However, their protocol does not provide user identification and suffers from the impersonation attack by malicious participants. In this paper, we propose improved ID-based AGKA protocol to prevent impersonation attack from Zhou et al.'s protocol. In our protocol, the malicious insider cannot impersonate another participants even if he knows the ephemeral group secret value. Moreover, our protocol reduces the computation cost from Zhou et al.'s protocol.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.1
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• pp.33-41
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• 2012

A differential fault analysis(DFA) is one of the most important side channel attacks on block ciphers. Most block ciphers, such as DES, AES, ARIA, SEED and so on., have been analysed by this attack. PRESENT is a 64-bit block cipher with 80/128-bit secret keys and has a 31-round SP-network. So far, several DFAs on PRESENT have been proposed. These attacks recovered 80, 128-bit secret keys of PRESENT with 8~64 fault injections. respectively. In this paper, we propose an improved DFA on PRESENT-80/128. Our attack can reduce the complexity of exhaustive search of PRESENT-80(resp. 128) to on average 1.7(resp. $2^{22.3}$) with 2(resp. 3) fault injections, From these results, our attack results are superior to known DFAs on PRESENT.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.12
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• pp.1250-1260
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• 2014

In this paper, a novel resource scheduling, which is used for hub network based long distance airborne tactical communication, is proposed. Recently, some countries of the world has concentrated on developing data rate and networking performance of CDL, striving to keep pace with modern warfare, which is changed into NCW. And our government has also developed the next generation high capacity CDL. In hub network, a typical communication structure of CDL, hybrid FDMA/TDMA can be considered to exchange high rate data among multiple UAVs simultaneously, within limited bandwidth. However, due to different RTT and traffic size of UAV, idle time resource and unnecessary packet transmission delay can occur. And these losses can reduce entire efficiency of hub network in long distance communication. Therefore, in this paper, we propose RTT and data traffic size based UAV scheduling, which selects time/frequency resource of UAVs by using iterative sorting algorithm. The simulation results verified that the proposed scheme improves data rate and packet delay performance in low complexity.

• Archives of design research
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• v.19 no.2 s.64
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• pp.121-128
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• 2006

The elements to enhance preference in symbol design are mainly related to consumers' response and aesthetic elements. Because certain aesthetic elements in design affect consumers' response and it is actually presented through (the different level of) preference. This study through surveying case studies examines whether a certain aesthetic element in symbol design gives rise to much preference. According to the result of study, high preference in symbolic design depends on high level of Rhythm, Balance, Harmony, Elaboration, Round, Gestalt, Organic, and Artificial/Natural among aesthetic elements. In comparison, it is founded that Simplicity/complexity, Objective/Abstract, depth, and symmetry should be designed at the moderate level, and proportion, repetition of elements be at the low level. Additionally(or Besides) this study makes out that symbol design cases with high preference have shapes from natural material or patterns of traditional culture, while cases with low preference have shapes from geometric figures. On the basis of these results, a guideline of symbol design could De offered(or suggested) to fit preference of consumers. But, this study is mostly concerned with only affect among emotional reactions of consumer in a scope of study, and is considered only in the aspect of form excluding color and texture.