• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.4
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• pp.116-128
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• 2011

In this paper, we propose the structure of a high-performance face-detection engine that responds well to facial rotating changes using rotation transformation which minimize the required memory usage compared to the previous face-detection engine. The validity of the proposed structure has been verified through the implementation of FPGA. For high performance face detection, the MCT (Modified Census Transform) method, which is robust against lighting change, was used. The Adaboost learning algorithm was used for creating optimized learning data. And the rotation transformation method was added to maintain effectiveness against face rotating changes. The proposed hardware structure was composed of Color Space Converter, Noise Filter, Memory Controller Interface, Image Rotator, Image Scaler, MCT(Modified Census Transform), Candidate Detector / Confidence Mapper, Position Resizer, Data Grouper, Overlay Processor / Color Overlay Processor. The face detection engine was tested using a Virtex5 LX330 FPGA board, a QVGA grade CMOS camera, and an LCD Display. It was verified that the engine demonstrated excellent performance in diverse real life environments and in a face detection standard database. As a result, a high performance real time face detection engine that can conduct real time processing at speeds of at least 60 frames per second, which is effective against lighting changes and face rotating changes and can detect 32 faces in diverse sizes simultaneously, was developed.

• Journal of the Korea Society of Computer and Information
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• v.24 no.12
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• pp.25-33
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• 2019

This paper presents a novel evolutionary framework for optimizing a bio-inspired fully dynamic neurocontroller for the maneuverable flapping flight of a simulated bird-sized ornithopter robot which takes advantage of the morphological computation and mechansensory feedback to improve flight stability. In order to cope with the difficulty of generating robust flapping flight and its maneuver, the wing of robot is modelled as a series of sub-plates joined by passive torsional springs, which implements the simplified version of feathers attached to the forearm skeleton. The neural controller is designed to have a bilaterally symmetric structure which consists of two fully connected neural network modules receiving mirrored sensory inputs from a series of flight navigation sensors as well as feather mechanosensors to let them participate in pattern generation. The synergy of wing compliance and its sensory reflexes gives a possibility that the robot can feel and exploit aerodynamic forces on its wings to potentially contribute to the agility and stability during flight. The evolved robot exhibited target-following flight maneuver using asymmetric wing movements as well as its tail, showing robustness to external aerodynamic disturbances.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.99-108
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• 2015

The embedded microcontroller which is operated by the logic gates synchronized on the clock pulse, is gradually used as main controller of mission-critical systems. Severe electrical situations such as high voltage/frequency surge may cause malfunctioning of the clock source. The tolerant system operation is required against the various external electric noise and means the robust design technique is becoming more important issue in system clock failure problems. In this paper, we propose on-chip backup clock change architecture for the automatic clock failure detection. For the this, we adopt the edge detector, noise canceller logic and glitch-free clock changer circuit. The implemented edge detector unit detects the abnormal low-frequency of the clock source and the delay chain circuit of the clock pulse by the noise canceller can cancel out the glitch clock. The externally invalid clock source by detecting the emergency status will be switched to back-up clock source by glitch-free clock changer circuit. The proposed circuits are evaluated by Verilog simulation and the fabricated IC is validated by using test equipment electrical field radiation noise

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.6
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• pp.293-303
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• 2008

As the computing environment moves to the wireless and handheld system, the power efficiency is getting more important. That is the case especially in the embedded hand-held system and the power consumed by the memory system takes the second largest portion in overall. To save energy consumed in the memory system we can utilize low power mode of SDRAM. In the case of RDRAM, nap mode consumes less than 5% of the power consumed in active or standby mode. However hardware controller itself can't use this facility efficiently unless the operating system cooperates. In this paper we focus on how to minimize the number of active units of SDRAM. The operating system allocates its physical pages so that only a few units of SDRAM need to be activated and the unnecessary SDRAM can be put into nap mode. This work can be considered as a generalized and system-wide version of PAVM(Power-Aware Virtual Memory) research. We take all the physical memory into account, especially buffer cache, which takes an half of total memory usage on average. Because of the portion of buffer cache and its importance, PAVM approach cannot be robust without taking the buffer cache into account. In this paper, we analyze the RAM usage and propose power-aware page allocation policy. Especially the pages mapped into the process' address space and the buffer cache pages are considered. The relationship and interactions of these two kinds of pages are analyzed and exploited for energy saving.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.41 no.7
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• pp.575-583
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• 2017

This paper describes the design and evaluation of a driving mode decision algorithm for automated driving for merge situations on highways. For the development of a highly automated driving control algorithm for merge situations, the driving mode decision is crucial for merging appropriately. There are two driving modes: lane keeping and lane changing (merging). The merge mode decision is determined based on the state of the surrounding vehicles and the remaining length of the merge lane. In the merge mode decision algorithm, merge possibility and the desired merge position are decided to change the lane safely and quickly. A safety driving envelope is defined based on the desired driving mode using the information on the surrounding vehicles' behaviors. To obtain the desired steering angle and longitudinal acceleration for maintaining the subject vehicle in the safe driving envelope, a motion planning controller is designed using model predictive control (MPC), with constraints that are decided considering the vehicle dynamics, safe driving envelope, and actuator limit. The proposed control algorithm has been evaluated via computer simulation studies.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.1
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• pp.98-106
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• 2001

This paper presents external load disturbance compensation that used to deadbeat load torque observer and regulation of the compensation gain by parameter estimator. As a result, the response of PMSM follows that of the nominal plant. The load torque compensation method is compose of a dead beat observer that is well-known method. However it has disadvantage such as a noise amplification effect. To reduce of the effect, the post-filter, which is implemented by MA process, is proposed. The parameter compensator with RLSM(recursive least square method) parameter estimator is suggested to increase the performance of the load torque observer and main controller. Although RLSM estimator is one of the most effective methods for online parameter identification, it is difficult to obtain unbiased result in this application. It is caused by disturbed dynamic model with external torque. The proposed RLSM estimator is combined with a high performance torque observer to resolve the problems. As a result, the proposed control system becomes a robust and precise system against the load torque and the parameter variation. A stability and usefulness, through the verified computer simulation and experiment, are shown in this paper.

• Journal of the Institute of Convergence Signal Processing
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• v.20 no.1
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• pp.16-23
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• 2019

Fine particulate matter known as PM 2.5 refers to the atmospheric particulate matter that has a diameter less than 2.5 micrometer identified as dangerous element for human health and its concentration can provide us a clear picture about air dust concentration. Humans stay indoor almost 90% of their life time and also there is no official indoor dust concentration data, so our study is focused on measuring the indoor air quality. Indoor dust data monitoring is very important in hospital environments beside that other places can also be considered for monitoring like classrooms, cements factories, computer server rooms, petrochemical storage etc. In this paper, visible light communication system is proposed by Manchester encoding technique for electromagnetic interference (EMI)-free indoor dust monitoring. Important indoor environment information like dust concentration is transferred by visible light channel in wide range. An average voltage-tracking technique is utilized for robust light detection to eliminate ambient light and low-frequency noise. The incoming light is recognized by a photo diode and are simultaneously processed by a receiver micro-controller. We can monitor indoor air quality in real-time and can take necessary action according to the result.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.1
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• pp.59-70
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• 2022

In this paper, we proposed an active fault tolerant control (AFTC) method for the position control of a quadrotor with complete loss of effectiveness of one motor. We obtained the dynamics of a quadrotor using Lagrangian equation without small angle assumption. For detecting the fault on a motor, we designed a fault detection module, which consists of the fault detection and diagnosis (FDD) module and the fault detection and isolation (FDI) module. For the FDD module, we designed a nonlinear observer that observes the states of a quadrotor based on the obtained dynamics. Using the observed states of a quadrotor, we designed residual signals and set the appropriate threshold values of residual signals to detect the fault. Also, we designed an FDI module to identify the fault location using the designed additional conditions. To make a quadrotor track the desired path after detecting the fault of a motor, we designed a fault tolerant controller based on the multiple sliding surface control (MSSC) technique. Finally, through simulations, we verified the effectiveness of the proposed AFTC method for a quadrotor with complete loss of effectiveness of one motor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.58-67
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• 2009

This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within $10{\mu}s$. It is implemented in a $0.18{\mu}m$ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8 nV/$\sqrt{Hz}$ input referred noise, and 5-dBm $IIP_3$ at 60-mW power consumption. The power detector shows the 35dB dynamic range for 100 MHz input.