• Communications of the Korean Institute of Information Scientists and Engineers
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• v.24 no.3 s.202
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• pp.35-42
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• 2006

본 논문에서는 내장형 소프트웨어 시스템, 특히 로봇 소프트웨어를 위한 self-managed 소프트웨어 개발 프레임워크로서 SHAGE 프레임워크를 제안하였다. SHAGE 프레임워크는 소프트웨어를 실행시간에 동적으로 변경시킬 수 있도록 지원하는 여러 모듈로 구성되어 있다. Observer가 외부 상황을 관찰하고 관찰된 상황이 Architecture Broker로 전달되면 후보 아키텍처 재구성 전략을 검색하고 Component Broker가 구체화 컴포넌트들을 검색한 후 상황에 적절한 아키텍처 재구성 전략과 컴포넌트 구성을 Decision Maker가 선택한다. Reconfigurator가 선택된 전략과 컴포넌트 구성을 기초로 로봇의 아키텍처를 재구성한다. 적응행위를 Evaluator가 평가하고 그 결과를 Learner가 축적하여 나중에 Decision Maker가 사용할 수 있게 한다. 프레임워크의 효용성을 확인하기 위해서 실제 로봇을 이용한 사례연구를 수행하였고, 이 실험을 통해 적응 과정을 확인하였다. 로봇은 상황과 사용자의 피드백에 적응하였다.

• Proceedings of the KSME Conference
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• 2004.11a
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• pp.579-584
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• 2004

In this paper, we present the mechanical, electrical system design and system integration of controllers including sensory devices of the humanoid, KHR-2 (KAIST Humanoid Robot - 2). We have developed KHR-2 since 2003. Total number of DOF of KHR-2 is 41. Each arm including a hand has 11 DOF and each leg has 6 DOF. Head and trunk also has 6 DOF and 1 DOF respectively. In head, two CCD cameras are used for eye. To control all axes efficiently, distributed control architecture is used to reduce computation burden of main controller and to expand devices easily. So we developed the sub-controller as a servo motor controller and a sensor interfacing devices using microprocessor. The main controller attached its back communicates with sub-controllers in real-time by CAN (Controller Area Network) protocol. We used Windows XP as its OS (Operation System) for fast development of main control program and easy extension of peripheral devices. And RTX HAL extension commercial software is used to realize the real-time control in Windows XP environment.

• International journal of advanced smart convergence
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• v.9 no.4
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• pp.173-178
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• 2020

As the fourth industrial revolution, in which people, objects, and information are connected as one, various fields such as smart energy, smart cities, artificial intelligence, the Internet of Things, unmanned cars, and robot industries are becoming the mainstream, drawing attention to big data. Among them, Smart Grid is a technology that maximizes energy efficiency by converging information and communication technologies into the power grid to establish a smart grid that can know electricity usage, supply volume, and power line conditions. Smart meters are equient that monitors and communicates power usage. We start with the goal of building a virtual smart grid and constructing a virtual environment in which real-time data is generated to accommodate large volumes of data that are small in capacity but regularly generated. A major role is given in creating a software/hardware architecture deployment environment suitable for the system for test operations. It is necessary to identify the advantages and disadvantages of the software according to the characteristics of the collected data and select sub-projects suitable for the purpose. The collected data was collected/loaded/processed/analyzed by the Hadoop ecosystem-based big data platform, and used to predict power demand through deep learning.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1895_1896
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• 2009

본 논문에서는 로봇 소프트웨어 컴포넌트 테스팅 자동화에 적합한 테스팅 자동화 프레임워크 및 계층적 로봇 소프트웨어 테스트 모델을 제안한다. 테스팅 자동화 프레임워크는 로봇 소프트웨어 컴포넌트의 지속적인 통합, 다양한 로봇 환경 및 분산 컴포넌트 환경을 지원한다. 테스팅 자동화 프레임워크를 실제 구현하여 테스트 베드에 설치 및 평가를 통하여, 본 논문에서 제안하는 프레임워크가 효율적임을 보인다.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10a
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• pp.770-775
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• 1987

In this paper, design and development experiences of a vision based robotic assembly system for electronic components are described. Specifically, the overall system consists of the following three subsystems each of which employs a 16 bit Preprocessor MC 68000 : supervisory controller, real-time vision system, and servo system. The three microprocessors are interconnected using the time shared common memory bus structure with hardwired bus arbitration scheme and operated as a master-slave type in which each slave is functionally fixed in view of software. With this system architecture, the followings are developed and implemented in this research; (i) the system programming language, called 'CLRC', for man-machine interface including the robot motion and vision primitives, (ii) real-time vision system using hardwired chain coder, (iii) the high-precision servo techniques for high speed de motors and high speed stepping motors. The proposed control system were implemented and tested in real-time successfully.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06a
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• pp.313-315
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• 2006

Robot Software Communication Architecture는 URC 로봇을 위해서 제안된 표준 시스템 소프트웨어 구조이다. RSCA용 응용 프로그램은 다수의 컴포넌트의 결합으로 구성되는데 RSCA의 기반이 된 SCA에서는 컴포넌트를 프로세스고 실행할 것인지 쓰레드로 실행할 것인지에 대해서 명확하게 정의하고 있지 않다. 만약 각각의 컴포넌트의 특성을 고려하여 어떻게 실행할 깃인지에 대한 부가적인 정보를 기술하고 이 정보에 따라서 컴포넌트를 실행하게 된다면, 보다 효율적으로 응용 프로그램을 실행할 수 있게 된다. 본 논문에서는 RSCA를 확장하여 컴포넌트의 실행에 대한 정보를 기술하는 방법 및 기술된 정보에 따라서 컴포넌트를 실행하기 위한 방법을 제시한다.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2404-2406
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• 2002

기존의 로봇은 주로 예측 가능한 환경 하에서 동작해왔다. 그러나 로봇의 적용분야가 확대되면서 예측하기 힘든 복잡한 자극에 대해 반응하도록 요구되고 있다. 복잡한 자극은 동일시간에 여러 가지 자극이 존재하는 공간적 복잡성과, 각기 다른 시간에 자극이 연속적으로 배열된 시간적 복잡성을 가진다. 기존의 로봇은 복잡한 자극에 대한 대처능력이 취약하다. 이러한 환경에서 적응할 수 있도록 여러 방면의 연구가 진행되어 왔으며, 그 중에서 동물이 환경의 변화에 대처하는 방법에 관한 많은 연구들이 진행되고 있다. 본 논문에서는 시간적 복잡성을 가진 자극에 반응하고 이를 학습하기 위해 HMM(Hidden Markov Model)을 이용한 시계열 학습구조를 제안한다. 또한 기본적인 행동선택 및 학습을 위해 동물의 행동선택을 모델링한 구조를 구현하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10c
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• pp.343-345
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• 2003

현재 대부분의 로봇 제어용 네트웍으로는 FieldBus 등이 사용되고 있다. 그러나 로봇 시스템의 고성능화와 다양한 기능으로 인하여 기존의 FieldBus가 제공하던 기능으로는 대역폭에서나 성능면에서 부족한 점이 나타나고 있다. IEEE1394는 이러한 로봇 제어용 네트웍에 매우 적합한 특성을 갖고 있다. 본 논문에서는 IEEE1394가 로봇 제어용 네트웍에 사용될 때 가질 수 있는 실시간성과 신뢰성 특징에 대해 분석해보고, IEEE1394의 특성을 잘 살릴 수 있는 제어용 소프트웨어 구조에 대해 연구하고 이를 구현한다. 실시간성 데이터를 위해서는 우선순위 큐를 이용한 패킷 전송방법을, 주기적 데이터를 위해서 등시성 전송방법을 이용한다.

• Electronics and Telecommunications Trends
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• v.20 no.2 s.92
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• pp.1-13
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• 2005

비구조화되고 예측 불가능한 환경에서 동작하는 지능형 로봇의 제어를 위한 프로그램의 개발은 범용 컴퓨터에서 수행되는 일반 응용프로그램과는 달리 로봇이 존재하는 세계와의 복잡한 상호작용을 전제로 하고 있다. 이러한 전제는 로봇 프로그램에게 순차성과 더불어 병행성, 예외처리, 외부세계와의 인터페이스 등을 요구하며 더불어 로봇소프트웨어 제어구조가 특정 하드웨어나 플랫폼에 의존적이지 않고 여러 하드웨어 플랫폼에 두루 적용될 수 있는 구조가 요구된다. 로봇 소프트웨어 아키텍처는 이러한 요구에 기반하여 프로그래밍의 복잡성과 반복성을 줄이고 로봇을 보다 효율적으로 제어할 수 있는 구조를 제공하는 것을 목적으로 한다. 본 논문에서는 로봇 소프트웨어 아키텍처에 대한 최근의 연구동향에 대하여 살펴보고 신성장동력의 하나인 IT 기반 지능형서비스 로봇을 위한 로봇 소프트웨어 아키텍처의 최근의 연구현황에 대하여 소개한다.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}