• Journal of Institute of Control, Robotics and Systems
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• v.13 no.5
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• pp.429-433
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• 2007

A number of techniques have been developed for estimation of speed or position in motor drives. The accuracy of these techniques is affected by the variation of motor parameters such as the stator resistance, stator inductance or torque constant. This paper is proposed a neural network based estimator for torque and ststor resistance in IPMSM Drives. The neural weights are initially chosen randomly and a model reference algorithm adjusts those weights to give the optimum estimations. The neural network estimator is able to track the varying parameters quite accurately at different speeds with consistent performance. The neural network parameter estimator has been applied to slot and flux linkage torque ripple minimization of the IPMSM. The validity of the proposed parameter estimator is confirmed by the operating characteristics controlled by neural networks control.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.207-209
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• 2006

A number of techniques have been developed for estimation of speed or position in motor drives. The accuracy of these techniques is affected by the variation of motor parameters such as the stator resistance, stator inductance or torque constant. This paper is proposed a neural network based estimator for torque and ststor resistance in IPMSM Drives. The neural weights are initially chosen randomly and a model reference algorithm adjusts those weights to give the optimum estimations. The neural network estimator is able to track the varying parameters quite accurately at different speeds with consistent performance. The neural network parameter estimator has been applied to slot and flux linkage torque ripple minimization of the IPMSM. The validity of the proposed parameter estimator is confirmed by the operating characteristics controlled by neural networks control.

• Journal of IKEEE
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• v.21 no.3
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• pp.264-267
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• 2017

In this paper, A low dropout (LDO) regulator that improves the power supply rejection ratio by using a noise canceling circuit is proposed. The noise rejection circuit between the error amplifier and the pass transistor is designed to reduce the influence of the pass transistor on the noise coming from the voltage source. The LDO regulator has the same regulation characteristics as the conventional LDO regulator. The proposed circuit uses 0.18um process and Cadence's Virtuoso and Specter simulator.

• Proceedings of the KIPE Conference
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• 2002.11a
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• pp.125-128
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• 2002

In this paper, a novel on-line do capacitance estimation method for the PWM converter is proposed. At no load, Input current at a low frequency is injected, which causes do voltage ripple. With the ac voltage and current ripple components of the dc side, the capacitance can be calculated. Experimental result shows that the estimation error is less than $2\%$.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1343-1345
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• 2005

In this paper, control schemes are proposed for a propulsion system(Converter/Inverter) of the TTX(Tilting Train express). In developed traction converter, unity power factor control, compensation method of dc link voltage have been applied. Output current of converter contains harmonics ripple at twice input ac line frequency, which causes a ripple in the dc link voltage so that control scheme is developed in inverter system to reduce the pulsating torque current. At low speed region, vector control scheme is applied and slip frequency control is adopted at high speed region. The performance of propulsion system will be verified by simulation and prototype experimental results.

• Proceedings of the KAIS Fall Conference
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• 2004.06a
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• pp.193-197
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• 2004

The four-leg Voltage Source Converter(VSC) can use the DC link voltage effectively by the 3-D SVPWM method. Hence the DC battery voltage can be reduced by $15\%$ in comparison to that of the conventional line-interactive UPS system. In this paper a novel line interactive Uninterruptible Power Supply(UPS) using the two four-leg VSCs is proposed. One VSC is in parallel with the ac link reactor of the power source side, and the other is in series with the load. The parallel four-leg voltage source inverter controls the three-phase line voltage independently in order to control the line reactor current indirectly. It eliminates the neutral line current and the active ripple power of the source side using the pqr theory so that unity power factor and the sinusoidal source current can be achieved even though both the source and the load voltages have zero sequence components. The series four-leg voltage source inverter compensates the line voltage and allows it to be balanced and harmonic-free. Both of the parallel and series four-leg voltage source inverters always act as independently controllable voltage sources, so that the three-phase output voltage shows a seamless transition to the backup mode. The feasibility of the proposed UPS system has been investigated and verified through computer simulations results.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.2
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• pp.154-162
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• 2000

A technique to suppress the low frequency ripple voltage of the DC output ${\gamma}$oltage in three-phase buck d diode rectifiers is presented in this paper. The proposed pulse frequency modulation method is employed to r regulate the output voltage of the buck diode rectifiers and guarantee zero-current switching of the switch over the Vvide load range. The pulse frequency control method used in tIns paper shows generally good p performance such as low THD of the input line current and unity power factor. In addition, the pulse f freιluency method can be effectively used to suppress the low frequency voltage ripple appeared in the dc output voltage. The proposed technique illustrates its validity and effectiveness through the respective s simulations and experiments.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.5
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• pp.401-408
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• 2012

A simple on-line elimination strategy of the dead time and inverter nonlinearity using the current slope information is presented for a PWM inverter-fed IPMSM (Interior Permanent Magnet Synchronous Motor) drive. In a PWM inverter-fed IPMSM drive, a dead time is inserted to prevent a breakdown of switching device. This distorts the inverter output voltage, resulting in a current distortion and torque ripple. In addition to the dead time, inverter nonlinearity exists in switching devices of the PWM inverter, which is generally dependent on operating conditions such as the temperature, DC link voltage, and current. The proposed scheme is based on the fact that the d-axis current ripple is mainly caused by the dead time and inverter nonlinearity. To eliminate such an influence, the current slope information is determined. The obtained current slope information is processed by the PI controller to estimate the disturbance caused by the dead time and inverter nonlinearity. The overall system is implemented using DSP TMS320F28335 and the validity of the proposed algorithm is verified through the simulation and experiments. Without requiring any additional hardware, the proposed scheme can effectively eliminate the dead time and inverter nonlinearity even in the presence of the parameter uncertainty.

• Journal of electromagnetic engineering and science
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• v.6 no.2
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• pp.110-116
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• 2006

A reflective array type surface acoustic wave(SAW) dispersive delay line(DDL) with high time-bandwidth at the V/UHF-band is designed and fabricated for compressive receiver applications. This type of the SAW DDL has the properties of the relative bandwidth of 20 %, the time delay of 49.89 usec, the insertion loss of 38.5 dB and the side lobe rejection of 39 dB. In comparison with a commercial SAW DDL, the insertion loss, amplitude ripple and side lobe rejection are improved by $1.5dB{\pm}0.6dB$ and 4 dB respectively. Using the fabricated SAW DDL, the prototype of the compressive receiver is developed. It is composed of RF converter, fast tunable LO, chirp LO, A/D converter, signal processing unit and control unit. This prototype system shows a fine frequency resolution of below 30 kHz with high scan rate.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.58 no.4
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• pp.483-489
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• 2009

Electrolytic capacitors are used in variety of equipments as smoothening element of the power converters because it has high capacitance for its size and low price. Electrolytic capacitors, which is most of the time affected by aging effect, plays a very important role for the power electronics system quality and reliability. Therefore it is important to estimate the parameter of an electrolytic capacitor to predict the failure. This objective of this paper is to propose a new method to detect the rise of equivalent series resistor(ESR) in order to realize the online failure prediction of electrolytic capacitor for DC output filter of power converter. The ESR of electrolytic capacitor estimated from RMS result of filtered waveform(BPF) of the ripple capacitor voltage/current. Therefore, the preposed online failure prediction method has the merits of easy ESR computation and circuit simplicity. Simulation and experimental results are shown to verify the performance of the proposed on-line method.