• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.7 no.4
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• pp.195-199
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• 2014

A bridge resistance deviation-to-period (BRD-to-P) converter is presented for interfacing resistive biosensors. It consists of a linear operational transconductance amplifier (OTA) and a current-controlled oscillator (CCO) formed by a current-tunable Schmitt trigger and an integrator. The free running period of the converter is 1.824 ms when the bridge offset resistance is $1k{\Omega}$. The conversion sensitivity of the converter amounts to $3.814ms/{\Omega}$ over the resistance deviation range of $0-1.2{\Omega}$. The linearity error of the conversion characteristic is less than ${\pm}0.004%$.

• ETRI Journal
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• v.29 no.1
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• pp.70-78
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• 2007

A new low-voltage CMOS interface circuit with digital output for piezo-resistive transducer is proposed. An input current sensing configuration is used to detect change in piezo-resistance due to applied pressure and to allow low-voltage circuit operation. A simple 1-bit first-order delta-sigma modulator is used to produce an output digital bitstream. The proposed interface circuit is realized in a 0.35 ${\mu}m$ CMOS technology and draws less than 200 ${\mu}A$ from a single 1.5 V power supply voltage. Simulation results show that the circuit can achieve an equivalent output resolution of 9.67 bits with less than 0.23% non-linearity error.

• Journal of IKEEE
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• v.23 no.2
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• pp.636-641
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• 2019

A simple resistance deviation-to-time period converter is proposed for interfacing resistive half-bridge sensors. It consists of two 2nd generation current conveyors(CCIIs). The proposed converter has simpler circuit configuration than the conventional converters using operational amplifiers or operational transconductance amplifiers(OTAs). The proposed converter was simulated using CCII implemented with AD844 IC chips. The simulation results show that the converter has a conversion sensitivity of $0.01934ms/{\Omega}$ over a range of $100-500{\Omega}$ resistance deviations and a linearity error less than ${\pm}0.002%$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.7 no.1
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• pp.40-44
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• 2014

A bridge resistance deviation-to-period (BRD-to-P) converter is presented for interfacing resistive biosensors. It consists of a linear operational transconductance amplifier (OTA) and a current-controlled oscillator (CCO) formed by a current-tunable Schmitt trigger and an integrator. The free running period of the converter is 1.824 ms when the bridge offset resistance is $1k{\Omega}$. The conversion sensitivity of the converter amounts to $3.814ms/{\Omega}$ over the resistance deviation range of $0-1.2{\Omega}$. The linearity error of the conversion characteristic is less than ${\pm}0.004%$.

• Journal of IKEEE
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• v.12 no.3
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• pp.167-171
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• 2008

A bridge resistance deviation-to-frequency (BRD-to-F) converter is presented for interfacing resistive sensor bridges. It consists of a linear operational transconductance amplifier (LOTA), a current-controlled oscillator (CCO). The prototype converter was simulated using commercially available discrete components. The result shows that the converter has a conversion sensitivity amounting to 16.90 kHz/${\Omega}$ and a linearity error less than ${\pm}$0.03 %.

• Proceedings of the KIEE Conference
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• 1987.11a
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• pp.527-529
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• 1987

This paper presents a study on the driving characteristics or delta inverter driving induction motor control systems based on the microprocessor. Delta inverter is a novel circuit which uses only three power transistor. Requiring approximately hair the components or a conventional bridge inverter it therefore has a merit of coat and Simplicity. The basic operating principles of the delta inverter and conventional bridge inverter are argued, using resistive and inductive load. Sinusoidal PWM method uses to reduce the harmonic components of its output waveform to acceptable levels.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1074-1086
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• 2019

This paper presents the design and implementation of an improved cascaded multilevel inverter topology with asymmetric DC sources. This experimental inverter topology is a stand-alone system with simulations and experiments performed using resistance loads. The topology uses four asymmetric binary DC sources that are independent from each other and one H-bridge. The topology was simulated using PSIM software before an actual prototype circuit was tested. The proposed topology was shown to be very efficient. It was able to generate a smooth output waveform up to 31 levels with only eight switches. The obtained simulation and experimental results are almost identical. In a 1,200W ($48.3{\Omega}$) resistive load application, the THDv and efficiency of the topology were found to be 1.7% and 97%, respectively. In inductive load applications, the THDv values were 1.1% and 1.3% for an inductive load ($R=54{\Omega}$ dan L=146mH) and a 36W fluorescent lamp load with a capacitor connected at the dc bus.

• Journal of Power Electronics
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• v.15 no.3
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• pp.741-752
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• 2015

This study proposes a new solution for the parallel operation of microgrid inverters in terms of circuit topology and control structure. A combined three-phase four-wire inverter composed of three single-phase full-bridge circuits is adopted. Moreover, the control structure is based on adaptive three-order sliding-mode control and wireless load-sharing control. The significant contributions are as follows. 1) Adaptive sliding-mode control performance in inner voltage loop can effectively reject both voltage and load disturbances. 2) Virtual resistive-output-impedance loop is applied in intermediate loop to achieve excellent power-sharing accuracy, and load power can be shared proportionally to the power rating of the inverter when loads are unbalanced or nonlinear. 3) Transient droop terms are added to the conventional power outer loop to improve dynamic response and disturbance rejection performance. Finally, theoretical analysis and test results are presented to validate the effectiveness of the proposed control scheme.