• 한국전자통신학회논문지
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• 제16권3호
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• pp.451-456
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• 2021

반도체 메모리 소자의 커패시터에서 셀 커패시턴스의 향상과 scale down을 위해 유전막으로써 적층형 ONO 구조가 도입되었고 이들의 박막화가 지속적으로 시도되고 있으나 공정 처리 과정에서 많은 문제들이 대두되고 있다. 본 연구에서는 L/L LPCVD를 사용하여 약 10Å의 자연산화막 성장을 억제함으로써 3fF/cell의 정전 용량을 확보할 수 있었다. 또한 유전막의 박막화에 따른 질화막의 이상산화에 미치는 영향을 고찰함으로써 내산화성을 확보할 수 있는 유전막 형성의 안정적인 공정 관리 방법을 제안하였다.

• 센서학회지
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• 제4권4호
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• pp.29-40
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• 1995

본논문(本論文)에서는 정전유도(靜電誘導) 트랜지스터의 잡음원인분석(雜音原因分析)을 위하여 직류(直流) 및 잡음특성(雜音特性), 잔존성분(殘存成分), 입력용량등(入力容量等)의 정무화(定武化)에 필요(必要)한 잡음(雜音) 등가회로(等價回路)를 제안(提案)하였다. 가장 단순(單純)한 잡음(雜音) 등가회로(等價回路)는 정전유도(靜電誘導) 트랜지스터의 동작원리(動作原理)에 의한 모델이며, 이 모델에 의한 실측치(實測値)가 산탄(shot) 잡음(雜音)보다 작게 나타났다. 소스 저항(抵抗)이 삽입(揷入)된 등가회로(等價回路)에서는 소스 저항(抵抗)의 부귀환효과(負歸還效果)에 의하여 산탄 잡음(雜音)이 저감(低減)됨을 확인(確認)하였다. 정확(正確)한 잡음저감원인(雜音低減原因)을 분석(分析)하기 위하여 소스 저항(抵抗)과 드레인 저항(低抗)의 계산식(計算式)을 유도(誘導)하기 위한 등가회로(等價回路)를 제안(提案)하였다. 등가회로(等價回路) 확인(確認) 실험(實驗)에서는 잔존성분(殘存成分)에 대한 신호원저항(信號源抵抗)과 출력부하저항(出力負荷抵抗)의 영향(影響)은 작으며, 잔존성분(殘存成分)은 입력환산등가잡음저항(入力換算等價雜音抵抗)으로 나타낼 수 있다. 또한, 입력용량(入力容量)은 부하저항(負荷抵抗)이 $0{\Omega}$일 때 13.6pF이며, 게이트 배선등(配線等) 정전유도(靜電誘導) 트랜지스터 동작(動作)에 직접(直接) 관여(關與)하지 않는 용량(容量)은 10pF정도(程度)이다.

• 한국세라믹학회지
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• 제45권8호
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• pp.493-496
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• 2008

Composite electrodes consisting of $CoMnO_2$ and carbon nanofibers(vapor grown carbon nanofiber, VGCF) with high electrical conducivity($CoMnO_2$/VGCF) were prepared on a porous nickel foam substrate as a current collector and their supercapacitive properties were investigated using cyclic voltammetry in 1 M KOH aqueous solution. The $CoMnO_2$/VGCF electrode exhibited high specific capacitance value of 630 F/g at 5 mV/s and excellent capacitance retention of 95% after $10^4$ cycles, indicating that the used VGCF played the important roles in reducing the interfacial resistance in the composite electrode to improve supercapacitive performance.

• 전력전자학회논문지
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• 제18권2호
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• pp.145-152
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• 2013

Electrolytic capacitors used for smoothing DC link voltage is one of the major root causes of fault in power electronic system. The aging of aluminum electrolytic capacitors is expressed by the increase of their equivalent series resistance (ESR) and the reduction of their capacitance. Thus, the proposed technique in this paper is to measure capacitance, by comparing energy loss of DC link capacitors with stator resistor in electric machine. Condition of DC link capacitors can be estimated from the capacitance decrease rate between initial and aged capacitors. The results show that the proposed technique provides an easy, widely applicable and simple low cost solution for detecting dc link capacitor degradation.

• 전기학회논문지P
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• 제54권4호
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• pp.163-170
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• 2005

This paper deals with an improved fault location algorithm with compensation ground capacitance through distributed parameter for a long parallel T/L. For the purpose of fault locating algorithm non-influenced by source impedance and fault resistance, the loop method was used in the system modeling analysis. This algorithm uses a positive and negative sequence of the fault current for high accuracy of fault locating calculation. Power system model of 160km and 300km long parallel T/L was simulated using EMTP software. To evaluate of the proposed algorithm, we used the several different cases 64 sampled data per cycle. The test results show that the proposed algorithm was minimized the error factor and speed of fault location estimation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 영호남학술대회 논문집
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• pp.216-221
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• 2000

This paper describes the analysis results on the PT ferroresonance at 154 kV GIS (gas Insulated substation by EMTP(Electro- magnetic Transient Program). We had simulated the PT ferroresonance between a potential transformer(PT) and an open circuit breaker's grading capacitance. The ferroresonance leads to very large power frequency overvoltages on PT bus and subsequent insulation failure. The large power can be supplied to the PT by the high voltage on the opened circuit due to the grading capacitance and equivalent capacitance of the buses during the ferroresonance. The damping circuit connected on the secondary winding were considered in the model. The actual countermeasure include a saturable inductor and a resistor series-mounted, but the 2 ohms of damping resistance was used in the computationl model.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 E
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• pp.2076-2079
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• 1999

This paper describes the analysis results on the PT ferroresonance at 154 kV GIS (gas Insulated substation by EMTP (Electro-magnetic Transient Program). We had simulated the PT ferroresonance between a potential transformer(PT) and an open circuit breaker's grading capacitance. The ferroresonance leads to very large power frequency overvoltages on PT bus and subsequent insulation failure. The large power can be supplied to the PT by the high voltage on the opened circuit due to the grading capacitance and equivalent capacitance of the buses during the ferroresonance. The damping circuit connected on the secondary winding were considered in the model. The actual countermeasure include a saturable inductor and a resistor series-mounted, but the 2 ohms of damping resistance was used in the computational model.

• 한국농공학회지
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• 제40권6호
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• pp.79-88
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• 1998

This study was conducted to measure the moisture content of soil using RF impedance in the range of 1 to 30MHz. Considering the water potential flow in the soils, two types of sensor such as parallel cylinder and perpendicular plate type were fabricated and tested. The capacitance and resistance of sonsors for soil samples having moisture content range of 2 to 27% were measured by Q-meter (HP4342). The higher soil moisture content was and the larger soil bulk density was, the more the capacitance of sensors increased. To eliminate the effect of bulk density on measuring soil moisture content using RF impedance, two kinds of model having the density independent functions such as the ratio of capacitance change to conductance change and weight of water and dry soils respectively were developed and estimated by regression analysis.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.173-176
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• 1999

Continuing improvement of microprocessor performance involves in the devece size. This allow greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However this has led to propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance(RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. Becase of pattering MSSQ (Methylsilsequioxane), we use RIE(Reactive ton Etching) which is a good anisotrgpy. In this study, according as we control a flow rate of CF$_4$/O$_2$ gas, RF power, we analysis by using ${\alpha}$ -step, SEM and AFM,

• 한국전자파학회논문지
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• 제15권6호
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• pp.590-598
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• 2004

저잡음 특성과 함께 부성 저항과 수동 캐패시턴스의 특성을 보이도록 설계된, 직렬 피드백 회로를 이용한 FET능동 캐패시턴스 회로를 심도 있게 분석하였고, 이를 저잡음 능동 대역통과 여파기에 적용하였다. 부성저항을 이용한 마이크로파 대역 능동 여파기의 설계방식은 비교적 여러 차례 소개되었으나, 원하는 주파수에서 적절한 부성저항 성분을 구현하는 데에는 아직 어려움이 있으며, 이로 인한 능동 회로의 안정성 저하와 대역내 평탄도 증가 등으로 인해 실제 상용화에는 다다르지 못하고 있다. 이들 문제를 해결하고 실제 상용화에 이르기 위해서는 부성저항 회로의 세밀한 분석이 필요하며, 이를 이용한 부성저항 성분의 제어를 가능하도록 해야 한다. 이에 본 논문에서는 능동 캐패시턴스 회로의 부성저항 성분을 분석하였고, 또한 BPF의 통과대역의 평탄도를 개선할 수 있는 방법을 제시하였다. 제작된 4단 대역통과 여파기는 중심주파수 1.99 ㎓에서 60 MHz의 대역폭을 가지며, 0.67 ㏈ 삽입손실, 0.3 ㏈ 이내의 대역내 평탄도와 3.0 ㏈의 잡음 지수 특성을 보였다.