• Title/Summary/Keyword: Resistance-capacitance

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Mathematical Modeling and Analysis for Water_Tree of Underground Cables (지중 케이블의 수트리에 대한 수학적 모델링 및 분석)

  • Lee, Jung-Woo;Oh, Yong-Taek
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.21 no.5
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    • pp.516-522
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    • 2020
  • Water trees can cause considerable damage to the performance of underground cables. Theymay formwithin the dielectric used in buried or water-immersed high voltage cables. They grow in a bush-like or tree-like form, often taking decades before causing damage to a cable's performance. They are usually found on very old underground cables, often in an inaccessible place. It is costly and time-consuming to detect watertrees in underground cables. Tree detection technology, including mathematical modeling,can reduce the maintenance cost and time necessary for detecting these trees.To simulate detection of water trees in this study, a mathematical model ofan XLPE cable and a water tree were developed. The complex water tree structure was simplified, based on two identified patterns of aventedtree. A Matlab simulation was performed to calculate and analyze the capacitance and resistance of a cable insulation layer,based on growth of a watertree. Capacitance size increased about 0.025×10-13[Farads/mm] compared to normal when the tree area of the cable was advanced to 95% of the insulation layer. The resistance value decreased by about 0.5×1016[ohm/m]. These changesand changesshowninaBurkes paper physical modeling simulation are similar.The value of mathematical modeling for detecting water trees and damage to underground cables has been demonstrated.

The study on DC-link Film Capacitor in 3 Phase Inverter System for the Consideration of Frequency Response (3상 인버터 시스템에서 주파수 특성을 고려한 필름 콘덴서의 DC-link 적용 방법에 관한 연구)

  • Park, Hyun-Soo
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.19 no.4
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    • pp.117-122
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    • 2018
  • A large-capacity three-phase system air conditioner recently includes an inverter circuit to reduce power consumption. The inverter circuit uses a DC voltage that comes from DC-link power capacitor with the function of rectifying, which means AC voltage to DC voltage using a diode. An electrolytic capacitor is generally used to satisfy the voltage ripple and current ripple conditions of a DC-link power capacitor used for rectifying. Reducing the capacitance of the capacitor decreases the size, weight, and cost of the circuit. This paper proposes an algorithm to reduce the input ripple current by combining the minimum point estimation phase locked loop (PLL) phase control and the average voltage d axis current control technique. When this algorithm was used, the input ripple current decreased by almost 90%. The current ripple of the DC-link capacitor decreased due to the decrease in input ripple current. The capacitor capacity can be reduced but the electrolytic capacitor has a heat generation problem and life-time limitations because of its large equivalent series resistance (ESR). This paper proposes a method to select a film capacitor considering the current ripple at DC-link stage instead of an electrolytic capacitor. The capacitance was selected considering the voltage limitation, RMS (Root Mean Square) current capacity, and RMS current frequency analysis. A $1680{\mu}F$ electrolytic capacitor can be reduced to a $20{\mu}F$ film capacitor, which has the benefit of size, weight and cost. These results were verified by motor operation.

Preparation of Bio-Chemical Sensor Electrodes by Using Electrical Impedance Properties of Carbon Nanotube Based Bulk Materials (탄소나노튜브 기반 벌크 소재의 전기적 임피던스 특성을 이용한 생화학 센서용 전극 개발 연구)

  • So, Dae-Sup;Huh, Hoon;Kim, Hee-Jin;Lee, Hai-Won;Kang, In-Pil
    • Applied Chemistry for Engineering
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    • v.21 no.5
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    • pp.495-499
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    • 2010
  • To develop chemical and biosensors, this paper studies sensing characteristics of bulk carbon nanotube (CNT) electrodes by means of their electrical impedance properties due to their large surface area and excellence chemical absorptivity. The sensors were fabricated in the form of film and nano web style by using composite process for mass production. The bulk composite electrodes were fabricated with singlewall and multi-wall carbon nanotubes based on host polymers such as Nafion and PAN, using a solution-casting and an electrospinning technique. The resistance and the capacitance of electrodes were measured with LCR meter under the various amounts of buffer solution to study the electrical impedance change properties of them. On the experimental of sensor electrode, impedance characteristics of the composite electrode are affected by its host polymer and nanofiller and its sensing response showed saturated result after applying some amounts of buffer solution for test chemical. Especially, the capacitance values showed drastic changes while the resistance values only changed within few percent range. It is deduced that the ions in the solution penetrated and diffused into the electrodes surface changed the electrical properties of the electrodes much like a doping effect.

Application of the Electrical Impedance of Rocks in Characterizing Pore Geometry (암석 내 공극구조의 평가를 위한 전기임피던스의 적용)

  • Choo, Min-Kyoung;Song, In-Sun;Lee, Hi-Kweon;Kim, Tae-Hee;Chang, Chan-Dong
    • The Journal of Engineering Geology
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    • v.21 no.4
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    • pp.323-336
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    • 2011
  • The hydro-mechanical behavior of the Earth's crust is strongly dependent on the fractional volume and geometrical structure of effective pore spaces. This study aims to understand the characteristics of pores using electrical impedance. We measured the electric impedance of core samples (diameter, 38-50 mm; length, 70-100 mm) of three types of granite (Hwangdeung, Pocheon, and Yangsan) and two types of sandstone (Boryung and Berea) with different porosities and pore structures, after saturation with saline water of varying salinities. The results show that resistance decreases but capacitance increases with increasing salinity of the pore fluid. For a given salinity, the resistivity and formation factor are reduced with increasing porosity of the rocks, and the capacitance increases. Berea sandstone shows anisotropy in resistance, tortuosity, and cementation factor, with these factors being highest normal to bedding planes. This result indicates that the connectivity of pores is weakest normal to bedding. In conclusion, the electrical characteristics of the tested samples are related not only to their porosity but also to the pore geometry.

Analysis of Capacitance and Mobility of ZTO with Amorphous Structure (비정질구조의 ZTO 박막에서 커패시턴스와 이동도 분석)

  • Oh, Teresa
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.20 no.6
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    • pp.14-18
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    • 2019
  • The conductivity of a semiconductor is primarily determined by the carriers. To achieve higher conductivity, the number of carriers should be high, and an energy trap level is created so that the carriers can cross the forbidden zone with low energy. Carriers have a crystalline binding structure, and interfacial mismatching tends to make them less conductive. In general, high-concentration doping is typically used to increase mobility. However, higher conductivity is also observed in non-orthogonal conjugation structures. In this study, the phenomena of higher conductivity and higher mobility were observed with space charge limiting current due to tunneling phenomena, which are different from trapping phenomena. In an atypical structure, the number of carriers is low, the resistance is high, and the on/off characteristics of capacitances are improved, thus increasing the mobility. ZTO thin film improved the on/off characteristics of capacitances after heat treating at $150^{\circ}C$. In charging and discharging tests, there was a time difference in the charge and discharging shapes, there was no distinction between n and p type, and the bonding structure was amorphous, such as in the depletion layer. The amorphous bonding structure can be seen as a potential barrier, which is also a source of space charge limiting current and causes conduction as a result of tunneling. Thus, increased mobility was observed in the non-structured configuration, and the conductivity increased despite the reduction of carriers.

Preparation of Graphite Oxide and its Electrochemical Double Layer Capacitor's Performances using Non-Aqueous Electrolyte (TEABF4 & TEMABF4) (산화흑연의 제조 및 전해질(TEABF4 & TEMABF4)에 따른 전기이중층 커패시터의 특성)

  • Yang, Sunhye;Kim, Ick-Jun;Jeon, Min-Je;Moon, Seong-In;Kim, Hyun-Soo;An, Kye-Hyeok;Lee, Yun-Pyo;Lee, Young-Hee
    • Applied Chemistry for Engineering
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    • v.18 no.3
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    • pp.291-295
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    • 2007
  • The oxidation treatment of needle cokes with 70 wt% of nitric acid and sodium chlorate ($NaClO_3$) was attempted to achieve an electrochemically active material with a large capacitance. The structure of needle cokes was changed to graphite oxide after oxidation treatment of needle cokes with acidic solution having the composition ratio, $NaClO_3$/needle cokes, of 7.5, and the inter-layer distance of the oxidized needle cokes was extended to $6.9{\AA}$with increasing oxygen content. On the other hand, the electrochemical performance of oxidized needle cokes as a polarized electrode for an Electric Double Layer Capacitor (EDLC) was examined with an electrolyte of 1.2 M $TEABF_4$ (tetraethylammonium tetrafluoroborate) and $TEABF_4$ (triethylmethylammonium tetrafluoroborate) in acetonitrile. The capacitor cell using 1.2 M $TEABF_4$/acetonitrile has exhibited smaller electric resistance of $0.05{\Omega}$, and larger capacitance per weight and volume of 32.0 F/g and 25.5 F/mL at the two-electrode system in the potential range 0~2.5 V than that of the capacitor cell using $TEABF_4$. The observed electrochemical performance was discussed with the correlation between the inter-layer distance in graphite oxide structure and the anionic size of electrolyte.

Impedance Spectroscopy Models for X5R Multilayer Ceramic Capacitors

  • Lee, Jong-Sook;Shin, Eui-Chol;Shin, Dong-Kyu;Kim, Yong;Ahn, Pyung-An;Seo, Hyun-Ho;Jo, Jung-Mo;Kim, Jee-Hoon;Kim, Gye-Rok;Kim, Young-Hun;Park, Ji-Young;Kim, Chang-Hoon;Hong, Jeong-Oh;Hur, Kang-Heon
    • Journal of the Korean Ceramic Society
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    • v.49 no.5
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    • pp.475-483
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    • 2012
  • High capacitance X5R MLCCs based on $BaTiO_3$ ceramic dielectric layers exhibit a single broad, asymmetric arc shape impedance and modulus response over the wide frequency range between 1 MHz to 0.01 Hz. Analysis according to the conventional brick-layer model for polycrystalline conductors employing a series connection of multiple RC parallel circuits leads to parameters associated with large errors and of little physical significance. A new parametric impedance model is shown to satisfactorily describe the experimental spectra, which is a parallel network of one resistor R representing the DC conductivity thermally activated by 1.32 eV, one ideal capacitor C exactly representing bulk capacitance, and a constant phase element (CPE) Q with complex capacitance $A(i{\omega})^{{\alpha}-1}$ with ${\alpha}$ close to 2/3 and A thermally activated by 0.45 eV or ca. 1/3 of activation energy of DC conductivity. The feature strongly indicate the CK1 model by J. R. Macdonald, where the CPE with 2/3 power-law exponent represents the polarization effects originating from mobile charge carriers. The CPE term is suggested to be directly related to the trapping of the electronic charge carriers and indirectly related to the ionic defects responsible for the insulation resistance degradation.

Frequency Characteristics of Anodic Oxide Films: Effects of Anodization Valtage

  • Lee, Dong-Nyung;Yoon, Young-Ku
    • Nuclear Engineering and Technology
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    • v.6 no.1
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    • pp.14-22
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    • 1974
  • Effects of anodization voltage on frequency characteristics of anodic oxide films on tantalum were analyzed based on the following impedance equatious : (equation omitted) Here $R_{f}$, $C_{f}$ and tan $\delta$$_{f}$ are equivalent series resistance in ohm, equivalent Belies capacitance in farad and dielectric loss, of anodic oxide films respectively Parameters P, $\tau$$_{ο}$, $\tau$$_{\omega}$, and Co are defined as follows: P=(d-w)/w, $\tau$$_{ο}$=$textsc{k}$$\rho$$_{ο}$, $\tau$$_{\omega}$=$textsc{k}$$\rho$$_{\omega}$, $C_{ο}$=$textsc{k}$A/d where d is the thickness of oxide film, $\omega$ is the diffusion layer thickness. $\rho$$_{ο}$ is the resistivity of oxide film at the interface of metal and the oxide, $\rho$$_{\omega}$ is the resistivity of oxide film at intrinsic region and A is the area of the film and $textsc{k}$=0.0885$\times$10$^{-12}$ $\times$dielectric constant, (in farad/cm). It was shown that dielectric loss and frequency dependence of equivalent series capacitance decrease as anodization voltage increases. This is a consequence of the fact that the thickness of diffusion layer increases a little with increasing anodization voltage whereas the total oxide thickness is proportional to the anodization voltage. The ngative deviation of measured values from tile relation, tan $\delta$$_{f}$=0.682 $\Delta$ $C_{f}$, was also discussed based on the Impedance equations given above. Here $\Delta$ $C_{f}$ is the change in capacitance between 0.1 and 1 KHZ.KHZ.Z.

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Dynamic Power Estimation Method of VLSI Interconnects (VLSI 회로 연결선의 동적 전력 소모 계산법)

  • 박중호;정문성;김승용;김석윤
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.2
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    • pp.47-54
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    • 2004
  • Up to the present, there have been many works to analyze interconnects on timing aspects, while less works have been done on power aspects. As resistance of interconnects and rise time of signals increase, power consumption associated with interconnects is ever-increasing. In case of clock trees, particularly power consumption associated with interconnects is over 30% of total power consumption. Hence, an efficient method to compute power consumption of interconnects is necessary and in this paper we propose a simple yet accurate method to estimate dynamic power consumption of interconnects. We propose a new reduced-order model to estimate power consumption of large interconnects. Through the proposed model which is directly derived from total capacitance and resistance of interconnects, we show that the dynamic power consumption of whole interconnects can be approximated, and propose an analytical method to compute the power consumption. The results applying the proposed method to various RC networks show that average relative error is 1.86% and maximum relative error is 9.82% in comparison with HSPICE results.

Design of the Adaptive Learning Circuit by Enploying the MFSFET (MFSFET 소자를 이용한 Adaptive Learning Curcuit 의 설계)

  • Lee, Kook-Pyo;Kang, Seong-Jun;Chang, Dong-Hoon;Yoon, Yung-Sup
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.8
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    • pp.1-12
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    • 2001
  • The adaptive learning circuit is designed on the basis of modeling of MFSFET (Metal-Ferroelectric-Semiconductor FET) and the numerical results are analyzed. The output frequency of the adaptive learning circuit is inversely proportional to the source-drain resistance of MFSFET and the capacitance of the circuit. The saturated drain current with input pulse number is analogous to the ferroelectric polarization reversal. It indicates that the ferroelectric polarization plays an important role in the drain current control of MFSFET. The output frequency modulation of the adaptive learning circuit is investigated by analyzing the source-drain resistance of MFSFET as functions of input pulse numbers in the adaptive learning circuit and the dimensionality factor of the ferroelectric thin film. From the results, the frequency modulation characteristic of the adaptive learning circuit are confirmed. In other words, adaptive learning characteristics which means a gradual frequency change of output pulse with the progress of input pulse are confirmed. Consequently it is shown that our circuit can be used effectively in the neuron synapses of nueral networks.

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