• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1183-1186
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• 2005

A new reset method for high contrast ratio and reduction of the reset time is presented. In this new reset method, except the first subfield, a new reset pulse with only ramp-up period is adopted. In this reset method, from the third subfield, the background luminance generated during the reset period is theoretically zero until the first subfield of the following frame. Employing the new reset method, the dark room contrast ratio improved to 3084.7:1 from 189.1:1 of the conventional reset method. The new reset method reduced the required time for reset per subfield to 160us except the first subfield.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2002.11a
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• pp.29-33
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• 2002

Period which does an electric condition of panel in reset in the driving method of PDP is reset period. This research experimentally analyzed the priming discharge characteristic of reset period. The amount of wall charge and the accumulation time accumulated by priming discharge are unrelated to width of priming pulse. And, self-erase discharge has the relation in the amount of wall charge by priming discharge. Then, it relates also to space charge generated by priming discharge. Moreover, space charge which helps self-erase discharge exists to about 22$mutextrm{s}$ after generating priming discharge. And, it is suitable within 12$mutextrm{s}$ of priming pulse width for efficient reset.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.756-759
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• 2003

We measure the spatiotemporal wall charge distributions on sustain and address electrodes during reset period in an ac PDP cell using the longitudinal electro-optic amplitude modulation method. We apply several reset waveforms like as ramp, exponentially growing and high voltage pulse, and compare the wall charge characteristics on address electrode as well as sustain electrodes for each reset waveforms.

• Journal of Information Display
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• v.2 no.1
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• pp.24-33
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• 2001

The characteristics of the reset and the address discharges of an alternating current Plasma Display Panel (ac PDP) were studied using 2-dimensional numerical discharge cell simulation. We investigated the wall charge variations during the reset discharge adopting ramping reset pulse and the subsequent addressing discharge. The roles of the ramping reset scheme can be divided into two stages, each electrode gathers wall charges during ramping-up of the initial stage and the built-up wall charges are lost during ramping-down of the later stage. Address discharge does not only change the wall charge distributions on the address and the scan electrodes but also on the sustain electrode. The increase in the wall charges on the sustain electrode was observed with the variation of the applied voltage to the sustain electrode during the address period. The increase of the applied voltage to the sustain electrode during the address period is expected to induce the decrease of the sustain voltage during the display period.

• Journal of Information Display
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• v.3 no.4
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• pp.13-18
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• 2002

In general, the background light that is produced during the reset period deteriorates the dark room contrast ratio in AC PDP. In this paper, we propose a modified ramp reset pulse that can reduce the background light to an imperceptible level. In the new reset waveform, the discharges between the scan and sustain electrodes are minimized by applying a positive bias voltage to the sustain electrode and only the weak discharges between the scan and address electrodes are found to occur during the reset period. We also adopted the MgO coated phosphor layer to improve the address voltage margin that was reduced when the bias voltage in the modified ramp reset waveform was applied. As a result, the address voltage margin of 45 V which is the same level of the conventional method was ortained and the dark room contrast ratio was improved up to 7500 : 1.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.57-60
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• 2002

This paper deals with the effect of ramp-type erase pulse waveform on the high temperature driving characteristics of ac PDP driven by ramp up-down reset waveform. The experimental results show that the discharge characteristics in the reset period are significantly affected by the erase pulse waveform and ambient temperature. The firing voltage is increased with ambient temperature. This can cause misfirings during the sustain period and should be avoided. As one of possible solutions, we propose the optimization of erasing pulse shape.

• ETRI Journal
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• v.30 no.5
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• pp.644-652
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• 2008

In this paper, a low-power CMOS interface circuit is designed and demonstrated for capacitive sensor applications, which is implemented using a standard 0.35-${\mu}m$ CMOS logic technology. To achieve low-power performance, the low-voltage capacitance-to-pulse-width converter based on a self-reset operation at a supply voltage of 1.5 V is designed and incorporated into a new interface circuit. Moreover, the external pulse signal for the reset operation is made unnecessary by the employment of the self-reset operation. At a low supply voltage of 1.5 V, the new circuit requires a total power consumption of 0.47 mW with ultra-low power dissipation of 157 ${\mu}W$ of the interface-circuit core. These results demonstrate that the new interface circuit with self-reset operation successfully reduces power consumption. In addition, a prototype wireless sensor-module with the proposed circuit is successfully implemented for practical applications. Consequently, the new CMOS interface circuit can be used for the sensor applications in ubiquitous sensor networks, where low-power performance is essential.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1544-1545
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• 2006

In this paper, we present a new reset waveform for a large-sustain-gap structure in at PDPs. In the driving of the large-sustain-gap structure with a conventional ramp reset waveform, we cannot avoid the condition of an address being a cathode, which causes lots of trouble in stabilizing a reset discharge. To solve these problems, we use the square pulse instead of the conventional rising ramp pulse. Before making a strong discharge between the address (cathode) and scan (anode) electrodes, we make a priming discharge between the address (anode) and the scan (cathode) electrodes to stabilize the strong discharge in which the address electrodes are the cathode. With this scheme, we obtained 60V minimum address voltage and 145V maximum address voltage in $250{\mu}m$ and $350{\mu}m$ gap structures.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.200-200
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• 2000

AC-PDP의 구동은 인가되는 Pulse의 파형에 의하여 결정된다. 이번 실험은 AC-PDP의 Subfield 파형중 Sustain 부분 첫 번째 Pulse의 폭(Width)에 변화를 주어 다음 Suatain Pulse 기간동안의 전기 광학적 특성을 구속 카메라와 전류의 변화를 통하여 측정하였으며 Sustain Pulse의 Rising Time을 변화 시켜 방전특성을 측정하였다. 이를 통하여 적합한 Sustain 구간의 초기조건을 예측하였으며, 적합한 Sustain Pulse를 찾아가는 실험 방법을 찾고자 하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.388-391
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• 2008

A new reset waveform with negative ramp pulse was proposed. Comparative experiments between the negative and positive waveforms were performed. During reset period, IR distributions and luminance of black and white conditions were measured with the 42-inch XGA PDP module. The negative waveform improved contrast ratio about 15.4 ~ 22.5 % than the positive waveform by lowing the black luminance in reset period. Z bias (= Vbb) of the positive waveform was 27 V higher than the negative waveform.