• Journal of Power Electronics
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• v.18 no.4
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• pp.965-974
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• 2018

A new zero-voltage-switching (ZVS) push-pull pulse-width modulation (PWM) converter is proposed in this paper. The wide ZVS condition for all of the switches is obtained by utilizing the energy stored in the output inductor and magnetizing inductance. As a result, the switching losses can be dramatically reduced. A simple auxiliary circuit including two small diodes and one capacitor is added at the secondary side of a high frequency (HF) transformer to reset the primary current during the circulating stage and to clamp the voltage spike across the rectifier diodes, which enables the use of low-voltage and low-cost diodes to reduce the conducting and reverse recovery losses. In addition, there are no active devices or resistors in the auxiliary circuit, which can be realized easily. A detailed steady operation analysis, characteristics, design considerations, experimental results and a loss breakdown are presented for the proposed converter. A 500 W prototype has been constructed to verify the effectiveness of the proposed concept.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.6
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• pp.15-20
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• 2019

Fundamental processes in digital forensic investigation - such as disk imaging - were developed when digital investigation was relatively young. As digital forensic processes and procedures matured, these fundamental tools, that are the pillars of the reset of the data processing and analysis phases of an investigation, largely stayed the same. This work is a study of modern digital forensic imaging software tools. Specifically, we will examine the feature sets of modern digital forensic imaging tools, as well as their development and release cycles to understand patterns of fundamental tool development. Based on this survey, we show the weakness in current digital investigation fundamental software development and maintenance over time. We also provide recommendations on how to improve fundamental tools.

• 한국초전도학회:학술대회논문집
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• v.10
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• pp.189-192
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• 2000

We fabricated rapid single-flux-quantum RS flip-flop circuits with and without Y$_1$Ba$_2$Cu$_3$O$_{7-{\delta}}$(YBCO) ground plane. The circuit consists of SNS-type ramp-edge Josephson junctions that have cobalt-doped YBCO and Sr$_2$AITaO$_6$(SAT) for barrier layer and insulator layer, respectively. The fabricated Josephson junction showed a typical RSJ-like current-voltage(I-V) characteristics above 50K. We sucessfuly demonstrated RS flip-flop at temperatures around 50K. The RS flip-flop fabricated on ground plane showed more definite set and reset state in voltage-flux(V-${\phi}$) modulation curve for read SQUID, which may be attributed to a shielding effect of the YBCO ground plane.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.378.1-378.1
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• 2014

In this study, we investigated that the resistance switching characteristics of Nb-doped HfO2 films with increasing Nb doping concentration. The Nb-doped HfO2 based ReRAM devices with a TiN/Nb-doped HfO2/Pt/Ti/SiO2 were fabricated on Si substrates. The Nb-doped HfO2 films were deposited by reactive dc magnetron co-sputtering at $300^{\circ}C$ and oxygen partial ratio of 60% (Ar: 16sccm, O2: 24sccm). Microstructure of Nb-doped HfO2 films and atomic concentration were investigated by XRD, TEM, and XPS, respectively. The Nb-doped HfO2 films showed set/reset resistance switching behavior at various Nb doping concentrations. The process voltage of forming/set is decreased and whereas the initial current level is increased in doped HfO2 films. However, the switching properties of Nb-doped HfO2 were changed above the specific doping concentration of Nb. The change of resistance switching behavior depending on doping concentration was discussed in terms of concentration of non-lattice oxygen and micro-structure of Nb-doped HfO2.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.2
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• pp.76-80
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• 2014

Dual-gate PCRAM which unify capacitor-less DRAM and NVM using a PCM instead of a typical SONOS flash memory is proposed as 1 transistor. $VO_2$ changes its phase between insulator and metal states by temperature and field. The front-gate and back-gate control NVM and DRAM, respectively. The feasibility of URAM is investigated through simulation using c-interpreter and finite element analysis. Threshold voltage of NVM is 0.5 V that is based on measured results from previous fabricated 1TPCM with $VO_2$. Current sensing margin of DRAM is 3 ${\mu}A$. PCM does not interfere with DRAM in the memory characteristics unlike SONOS NVM. This novel unified dual-gate PCRAM reported in this work has 1 transistor, a low RESET/SET voltage, a fast write/erase time and a small cell so that it could be suitable for future production of URAM.

• Journal of the Korea Society of Computer and Information
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• v.22 no.1
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• pp.1-7
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• 2017

In this paper, we propose an efficient method that is tracking an object in real time using particle filter and adaptive observation model. When tracking object, it happens object shape variation by camera or object movement in variety environments. The traditional method has an error of tracking from these variation, because it has fixed observation model about the selected object by the user in the initial frame. In order to overcome these problems, we propose a method that updates the observation model by calculating the similarity between the used observation model and the eight-way of edge model from the current position. If the similarity is higher than the threshold value, tracking the object using updated observation model to reset observation model. On the contrary to this, the algorithm which consists of a process is to maintain the used observation model. Finally, this paper demonstrates the performance of the stable tracking through comparison with the traditional method by using a number of experimental data.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.48-52
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• 2014

In this paper, scaling down characteristics of vertical channel phase random access memory are investigated with device simulator and finite element analysis simulator. Electrical properties of select transistor are obtained by device simulator and those of phase change material are obtained by finite element analysis simulator. From the fusion of both data, scaling properties of vertical channel phase change random access memory (VPCRAM) are considered with ITRS roadmap. Simulation of set reset current are carried out to analyze the feasibility of scaling down and compared with values in ITRS roadmap. Simulation results show that width and length ratio of the phase change material (PCM) is key parameter of scaling down in VPCRAM. Thermal simulation results provide the design guideline of VPCRAM. Optimization of phase change material in VPCRAM can be achieved by oxide sidewall process optimization.

• Journal of Korea Multimedia Society
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• v.25 no.9
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• pp.1257-1265
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• 2022

Recognition of sign language is challenging due to the occlusion of hands, accuracy of hand gestures, and high computational costs. In recent years, deep learning techniques have made significant advances in this field. Although these methods are larger and more complex, they cannot manage long-term sequential data and lack the ability to capture useful information through efficient information processing with faster convergence. In order to overcome these challenges, we propose a word-level sign language recognition (SLR) system that combines a real-time human pose detection library with the minimized version of the gated recurrent unit (GRU) model. Each gate unit is optimized by discarding the depth-weighted reset gate in GRU cells and considering only current input. Furthermore, we use sigmoid rather than hyperbolic tangent activation in standard GRUs due to performance loss associated with the former in deeper networks. Experimental results demonstrate that our pose-based optimized GRU (Pose-OGRU) outperforms the standard GRU model in terms of prediction accuracy, convergency, and information processing capability.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.410-410
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• 2013

Next-generation nonvolatile memory (NVM) has attracted increasing attention about emerging NVMs such as ferroelectric random access memory, phase-change random access memory, magnetic random access memory and resistance random access memory (RRAM). Previous studies have demonstrated that RRAM is promising because of its excellent properties, including simple structure, high speed and high density integration. Many research groups have reported a lot of metal oxides as resistive materials like TiO2, NiO, SrTiO3 and ZnO [1]. Among them, the ZnO-based film is one of the most promising materials for RRAM because of its good switching characteristics, reliability and high transparency [2]. However, in many studies about ZnO-based RRAMs, there was a problem to get lower current level for reducing the operating power dissipation and improving the device reliability such an endurance and an retention time of memory devices. Thus in this paper, we investigated that highly reproducible bipolar resistive switching characteristics of W doped ZnO RRAM device and it showed low resistive switching current level and large ON/OFF ratio. This may be caused by the interdiffusion of the W atoms in the ZnO film, whch serves as dopants, and leakage current would rise resulting in the lowering of current level [3]. In this work, a ZnO film and W doped ZnO film were fabricated on a Si substrate using RF magnetron sputtering from ZnO and W targets at room temperature with Ar gas ambient, and compared their current levels. Compared with the conventional ZnO-based RRAM, the W doped ZnO ReRAM device shows the reduction of reset current from ~$10^{-6}$ A to ~$10^{-9}$ A and large ON/OFF ratio of ~$10^3$ along with self-rectifying characteristic as shown in Fig. 1. In addition, we observed good endurance of $10^3$ times and retention time of $10^4$ s in the W doped ZnO ReRAM device. With this advantageous characteristics, W doped ZnO thin film device is a promising candidates for CMOS compatible and high-density RRAM devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.128-133
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• 2008

Phase-change random access memory (PRAM) chip cell phase of amorphous state is rapidly changed to crystal state above 160 Celsius degree within several seconds during Infrared (IR) reflow. Thus, on-board programming method is considered for PRAM chip programming. We demonstrated the functional 512Mb PRAM with 90nm technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme. The reverse-state standby current of each PRAM cell is near 10 pA range. The total leak current of 512Mb PRAM chip in standby mode on discharging state can be more than 5 mA. Thus in the proposed BLDIS control, all bitlines (BLs) are in floating state in standby mode, then in active mode, the activated BLs are discharged to low level in the early timing of the active period by the short pulse BLDIS control timing operation. In the conventional sense amplifier, the simultaneous switching activation timing operation invokes the large coupling noise between the VSAREF node and the inner amplification nodes of the sense amplifiers. The coupling noise at VSAREF degrades the sensing voltage margin of the conventional sense amplifier. The merit of the proposed sense amplifier is almost removing the coupling noise at VSAREF from sharing with other sense amplifiers.