• ETRI Journal
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• v.27 no.5
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• pp.525-532
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• 2005

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix-4, center to top, parallel decoding, and early-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field-programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.

• The Transactions of the Korea Information Processing Society
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• v.2 no.4
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• pp.603-610
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• 1995

In this paper, we present a highly efficient simulation package which supports simulation from functional level to gate level. The package consists of a set of front-end tools, a logic simulator, named HSIM(Highly efficient logic SIMulator), and an waveform analyzer. The front-end tools include a netlist compiler, functional primitive compiler and behavioral compiler. Key feature of developed simulator is that the compiled behavioral models written in C language are directly executed in the simulation engine using incremental loader. By doing so, we achieved significant speed up as compared with the interpretive functional simulator. Experimental results show that HSIM runs about 55% faster than traditional unit-delay event-driven interpretive simulator.

• Journal of the Korean Society for Heat Treatment
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• v.22 no.2
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• pp.95-100
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• 2009

In this study, the casting process using forged insert was investigated to characterize the manufacturing process by which good mechanical properties can be obtained when compared with existing casting products. Process analysis for the casting design was performed by using FVM (Finite Volume Method) software. In pouring process, three kinds of candidate gating systems are considered and analyzed respectively. The molten metal behavior in gating system is so important that it affects the solidification behavior of the cast. The results show that as the number of gates is increased, hardness of cast was increased and gaps of cast with forged insert were decreased.

• Transactions of the KSME C: Technology and Education
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• v.3 no.4
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• pp.307-312
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• 2015

The passenger boarding bridge which provides a safe and comfort passenger pathway between an airplane and airport terminal gate is one of the apron equipment. This study investigates the effect of the lift column layout design on structural strength of the passenger boarding bridge by using finite element method, comparing deflection and stress. The overlapped zone of the tunnel frame A and B occurred at the maximum stress. The results of this research show that the lift column layout design is closely the value of the maximum stress.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.5 no.4
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• pp.23-30
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• 1985

Dynamic pile-driving formulas are widely used in predicting the load capacity of piles in cohesionless soils. However, the accuracy of the formulas has been questioned for a long time due to their oversimplified assumptions and empirical parameters involved in the formulas. The allowable pile capacities calculated by 6 different dynamic pile-driving formulas are compared statistically with the capacities measured in the field, in this paper, to find out the correlations between the calculated capacities and the measured values. The statistical data are then used to evaluate and to adjust the formulas to improve their accuracy. For the greatest accuracy and simplicity of use, it is recommended that the adjusted form of Gates formula be used. When the result of this recommended formula is compared with that of the existing Olson's modified formula, the former is found to be conservative by more than 10 percents.

• ETRI Journal
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• v.16 no.4
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• pp.1-11
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• 1995

A GaAs power metal semiconductor field effect transistor (MESFET) operating at a voltage as low as 3.3V has been developed with the best performance for digital handheld phone. The device has been fabricated on an epitaxial layer with a low-high doped structure grown by molecular beam epitaxy. The MESFET, fabricated using $0.8{\mu}m$ design rule, showed a maximum drain current density of 330 mA/mm at $V_{gs}$ =0.5V and a gate-to-drain breakdown volt-age of 28 V. The MESFET tested at a 3.3 V drain bias and a 900 MHz operation frequency displayed an output power of 32.5-dBm and a power added efficiency of 68%. The associate power gain at 20 dBm input power and the linear gain were 12.5dB and 16.5dB, respectively. Two tone testing measured at 900.00MHz and 900.03MHz showed that a third-order intercept point is 49.5 dBm. The power MESFET developed in this work is expected to be useful as a power amplifying device for digital hand-held phone because the high linear gain can deliver a high power added efficiency in the linear operation region of output power and the high third-order intercept point can reduce the third-order intermodulation.

• ETRI Journal
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• v.29 no.3
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• pp.363-370
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• 2007

In this paper, we propose a flexible turbo decoding algorithm for a high order modulation scheme that uses a standard half-rate turbo decoder designed for binary quadrature phase-shift keying (B/QPSK) modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Iterative codes such as turbo codes process the received symbols recursively to improve performance. As the number of iterations increases, the execution time and power consumption also increase. The proposed algorithm reduces the latency and power consumption by combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implement the proposed scheme on a field-programmable gate array and compare its decoding speed with that of a conventional decoder. The results show that the proposed flexible decoding algorithm is 6.4 times faster than the conventional scheme.

• ETRI Journal
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• v.37 no.1
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• pp.97-106
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• 2015

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology, with $100{\mu}m$ width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).

• Design & Manufacturing
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• v.2 no.5
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• pp.5-10
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• 2008

Recently, ultra precision and light-weight micro products are needed in various industries. Injection molding products with metal insert material is often satisfied with light-weight and precision simultaneously. The researches on macro-size insert deformation have been performed but, a research on micro-size insert is meager. In this paper, the injection molding product with $300{\mu}m$ thin foil insert is designed and insert injection molding process is performed. Finally, the deformation of thin foil insert is analyzed according to insert feature and gate length.

• Journal of the Korean Society of Systems Engineering
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• v.13 no.2
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• pp.9-17
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• 2017

Concept development of a real-time Field Programmable Gate Array (FPGA)-based switched Ethernet data communication network for the Man-Machine Interface System (MMIS) is presented in this paper. The proposed design discussed in this research is based on the systems engineering (SE) approach. The design methodology is effectively developed by defining the concept development stage of the life-cycle model consisting of three successive phases, which are developed and discussed: needs analysis; concept exploration; and concept definition. This life-cycle model is used to develop an FPGA-based time-triggered Ethernet (TTE) switched data communication network for the non-safety division of MMIS system to provide real-time data transfer from the safety control systems to the non-safety division of MMIS and between the non-safety systems including control, monitoring, and information display systems. The original IEEE standard 802.3 Ethernet networks were not typically designed or implemented for providing real-time data transmission, however implementing a network that provides both real-time and on-demand data transmission is achievable using the real-time Ethernet technology. To develop the design effectively, context diagrams are implied. Conformance to the stakeholders needs, system requirements, and relevant codes and standards together with utilizing the TTE technology are used to analyze, synthesize, and develop the MMIS non-safety data communication network of the APR1400 nuclear power plant.