• 한국신뢰성학회:학술대회논문집
• /
• 한국신뢰성학회 2001년도 정기학술대회
• /
• pp.239-244
• /
• 2001

Today, Ultrasonic is used as an important non-destructive test tool of semiconductor reliability evaluation and failure analysis. The semiconductor packaging trend goes to develop thin package, this trend makes difficult to inspect to defect in semiconductor package. One of the important problem in all semiconductor is moisture absorption in the atmosphere. This moisture causes crack or delamination to package when the semiconductor package is soldered on PCB. Reliability evaluation of semiconductor's object is investigating the effect of this moisture. For that reason, this study is investigating the effect of this moisture and reliability evaluation of semiconductor after preconditioning test and scanning acoustic microscope.

• 한국재료학회지
• /
• 제19권5호
• /
• pp.288-292
• /
• 2009

This article shows various factors that influence the thermal-cycling reliability of semiconductor devices utilizing the lead-on-chip (LOC) die attach technique. This work details how the modification of LOC package design as well as the back-grinding and dicing process of semiconductor wafers affect passivation reliability. This work shows that the design of an adhesion tape rather than a plastic package body can play a more important role in determining the passivation reliability. This is due to the fact that the thermal-expansion coefficient of the tape is larger than that of the plastic package body. Present tests also indicate that the ceramic fillers embedded in the plastic package body for mechanical strengthening are not helpful for the improvement of the passivation reliability. Even though the fillers can reduce the thermal-expansion of the plastic package body, microscopic examinations show that they can cause direct damage to the passivation layer. Furthermore, experimental results also illustrate that sawing-induced chipping resulting from the separation of a semiconductor wafer into individual devices might develop into passivation cracks during thermal-cycling. Thus, the proper design of the adhesion tape and the prevention of the sawing-induced chipping should be considered to enhance the passivation reliability in the semiconductor devices using the LOC die attach technique.

• 한국정밀공학회지
• /
• 제16권3호통권96호
• /
• pp.25-29
• /
• 1999

The lead frame manufactured by press stamping process, is an important part of semiconductor. The recent technical trend of semiconductor, chip sized and high performance package technology, requires the lead frame to be of more multi-leads and of fine ILP (Inner Lead Pitch). As the ILP is getting finer, its corresponding punch of the stamping die is getting narrower. The punch narrower than its stamping limit has been broken due to local buckling. This paper analyzed the phenomena of punch breakdown. Moreover, the punch design was modified to increase the critical limit of buckling force. This paper, also, suggested new design rules of the punch, which asks the modification of its lead frame design that has to be considered in the stage of semiconductor package design. The new design rules of lead frame design yields a good reliability of semiconductor package as well as a good quality of lead frame.

• 마이크로전자및패키징학회지
• /
• 제13권4호
• /
• pp.1-7
• /
• 2006

WLCSP(wafer level chip size package)는 웨이퍼 레벨에서 패키지 공정이 이루어지는 차세대 패키지 중 하나이다. WLCSP는 웨이퍼 레벨에서 패키지 공정이 이루어진다는 특징으로 인하여 웨이퍼당 생산되는 반도체 칩의 수에 따라 그 패키징 비용을 크게 줄일 수 있다는 장점이 있다. 그러나 응력 버퍼 역할을 하는 기판을 없애는 혁신적인 구조로 인하여 솔더 조인트의 신뢰성이 기존의 BGA 패키지에 비하여 취약하게 되는데, 이러한 솔더 조인트 신뢰성에 대하여 반도체 칩과 솔더볼을 연결하는 폴리머 절연층은 열팽창계수 차이에 의해 발생하는 응력을 흡수하는 중요한 역할을 하게 된다. 본 연구에서는 하이닉스에서 개발한 Omega-CSP를 사용하여 솔더볼 배열 변화와 제 1 절연층의 특성에 따른 솔더 조인트의 열피로 특성을 평가하였다. 그 결과 절연층의 특성 변화가 솔더 조인트의 열피로 특성에 주는 영향은 솔더볼 배열 구조에 따라 변화되는 것을 확인하였다.

• 한국표면공학회지
• /
• 제43권3호
• /
• pp.142-147
• /
• 2010

We evaluated characteristics of ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) surface treatment for mobile equipment that requires high reliability, in addition to investigating surface treatment processes for semiconductor boards that require high reliability such as regular PCB-package systems, board-on-chip, chip-scaled package (CSP), etc and application for semiconductor package board of SIP, BOC. As a result, it appeared that ENEPIG has superior properties compared to ENIG surface treatment in corrosion resistance, solder junction, wetting, etc. We anticipate that these results will be able to lend credibility to ENEPIG as a low-cost alternative for producing mobile devices such as the cell phones, especially when applied to mass production.

• 마이크로전자및패키징학회지
• /
• 제18권2호
• /
• pp.35-41
• /
• 2011

Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
• /
• pp.53-56
• /
• 2004

This paper presents the improved burn-in method for the reliability of SRAM in MCP Semiconductor reliability is commonly improved through the burn-in process. Reliability problem is more significant in the Multi Chip Package, because of including over two devices in a package. In the SRAM-based Multi Chip Package, the failure of SRAM has a large effect on the yield and quality of the other chips - Flash Memory, DRAM, etc. So, the quality of SRAM must be guaranteed. To improve the quality of SRAM, we applied the improved wafer level burn-in process using multi cell selection method in addition to the current used methods. That method is effective in detecting special failure. Finally, with the composition of some kinds of methods, we could achieve the high qualify of SRAM in Multi Chip Package.

• 한국전기전자재료학회논문지
• /
• 제18권6호
• /
• pp.506-509
• /
• 2005

This paper presents the improved burn-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved by the burn-in process. Reliability Problem is very significant in the MCP which includes over two chips in a package because the failure of one SRAM chip has a large influence on the yield and quality of the other chips such as Flash Memory, DRAM, etc. Therefore the quality of SRAM must be guaranteed. To improve the qualify of SRAM, we applied the improved wafer level burn-in process using multi cell selection method in addition to the previously used methods and it is found to be effective in detecting particular failures. Finally, with the composition of some kinds of methods, we achieved the high quality of SRAM in MCP.

• 비파괴검사학회지
• /
• 제21권6호
• /
• pp.598-606
• /
• 2001

최근 전자장치의 고기능화에 따라서 반도체 장치의 고집적화는 물론 반도체 패키지의 박형화 추세에 있다. 이러한 반도체가 장치에 실장된 후에도 안정된 성능을 발휘할 수 있는지 여부에 대한 신뢰성을 보장하기 위해 조립 완료된 반도체 패키지에 대한 preconditioning 시험을 수행하게 된다. 또한 preconditioning 시험 전후에 초음파 주사 현미경을 이용한 검사를 실시함으로써 반도체 패키지에 대한 들뜸이나 패키지 크랙과 같은 내부 결함의 존재 여부를 알아보게 된다. 본 논문에서는 반도체 내부의 결함 유무를 효과적으로 검사할 수 있는 초음파를 이용한 신뢰성 평가 방법과 절차를 제시하고, preconditioning 시험 과정에서 수행되는 시험법을 통해 패키지 내부 결함을 야기하는 가장 중요한 요인이라 할 수 있는 수분에 의한 고장 메커니즘을 분명히 함으로써 반도체 패키지에 대한 일련의 고장 분석 및 신뢰성 평가 방법을 정립하고자 하였다.

• 한국마이크로전자및패키징학회:학술대회논문집
• /
• 한국마이크로전자및패키징학회 2007년도 SMT/PCB 기술세미나
• /
• pp.67-79
• /
• 2007