• Proceedings of the Korean Reliability Society Conference
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• 2001.06a
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• pp.239-244
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• 2001

Today, Ultrasonic is used as an important non-destructive test tool of semiconductor reliability evaluation and failure analysis. The semiconductor packaging trend goes to develop thin package, this trend makes difficult to inspect to defect in semiconductor package. One of the important problem in all semiconductor is moisture absorption in the atmosphere. This moisture causes crack or delamination to package when the semiconductor package is soldered on PCB. Reliability evaluation of semiconductor's object is investigating the effect of this moisture. For that reason, this study is investigating the effect of this moisture and reliability evaluation of semiconductor after preconditioning test and scanning acoustic microscope.

• Korean Journal of Materials Research
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• v.19 no.5
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• pp.288-292
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• 2009

This article shows various factors that influence the thermal-cycling reliability of semiconductor devices utilizing the lead-on-chip (LOC) die attach technique. This work details how the modification of LOC package design as well as the back-grinding and dicing process of semiconductor wafers affect passivation reliability. This work shows that the design of an adhesion tape rather than a plastic package body can play a more important role in determining the passivation reliability. This is due to the fact that the thermal-expansion coefficient of the tape is larger than that of the plastic package body. Present tests also indicate that the ceramic fillers embedded in the plastic package body for mechanical strengthening are not helpful for the improvement of the passivation reliability. Even though the fillers can reduce the thermal-expansion of the plastic package body, microscopic examinations show that they can cause direct damage to the passivation layer. Furthermore, experimental results also illustrate that sawing-induced chipping resulting from the separation of a semiconductor wafer into individual devices might develop into passivation cracks during thermal-cycling. Thus, the proper design of the adhesion tape and the prevention of the sawing-induced chipping should be considered to enhance the passivation reliability in the semiconductor devices using the LOC die attach technique.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.3 s.96
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• pp.25-29
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• 1999

The lead frame manufactured by press stamping process, is an important part of semiconductor. The recent technical trend of semiconductor, chip sized and high performance package technology, requires the lead frame to be of more multi-leads and of fine ILP (Inner Lead Pitch). As the ILP is getting finer, its corresponding punch of the stamping die is getting narrower. The punch narrower than its stamping limit has been broken due to local buckling. This paper analyzed the phenomena of punch breakdown. Moreover, the punch design was modified to increase the critical limit of buckling force. This paper, also, suggested new design rules of the punch, which asks the modification of its lead frame design that has to be considered in the stage of semiconductor package design. The new design rules of lead frame design yields a good reliability of semiconductor package as well as a good quality of lead frame.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.1-7
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• 2006

A major failure mode for wafer level chip size package (WLCSP) is thermo-mechanical fatigue of solder joints. The mechanical strains and stresses generated by the coefficient of thermal expansion (CTE) mismatch between the die and printed circuit board (PCB) are usually the driving force for fatigue crack initiation and propagation to failure. In a WLCSP process peripheral or central bond pads from the die are redistributed into an area away using an insulating polymer layer and a redistribution metal layer, and the insulating polymer layer affects solder joints reliability by absorption of stresses generated by CTE mismatch. In this study, several insulating polymer materials were applied to WLCSP to investigate the effect of insulating material. It was found that the effect of property of insulating material on WLCSP reliability was altered with a solder ball layout of package.

• Journal of the Korean institute of surface engineering
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• v.43 no.3
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• pp.142-147
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• 2010

We evaluated characteristics of ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) surface treatment for mobile equipment that requires high reliability, in addition to investigating surface treatment processes for semiconductor boards that require high reliability such as regular PCB-package systems, board-on-chip, chip-scaled package (CSP), etc and application for semiconductor package board of SIP, BOC. As a result, it appeared that ENEPIG has superior properties compared to ENIG surface treatment in corrosion resistance, solder junction, wetting, etc. We anticipate that these results will be able to lend credibility to ENEPIG as a low-cost alternative for producing mobile devices such as the cell phones, especially when applied to mass production.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.2
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• pp.35-41
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• 2011

Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.53-56
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• 2004

This paper presents the improved burn-in method for the reliability of SRAM in MCP Semiconductor reliability is commonly improved through the burn-in process. Reliability problem is more significant in the Multi Chip Package, because of including over two devices in a package. In the SRAM-based Multi Chip Package, the failure of SRAM has a large effect on the yield and quality of the other chips - Flash Memory, DRAM, etc. So, the quality of SRAM must be guaranteed. To improve the quality of SRAM, we applied the improved wafer level burn-in process using multi cell selection method in addition to the current used methods. That method is effective in detecting special failure. Finally, with the composition of some kinds of methods, we could achieve the high qualify of SRAM in Multi Chip Package.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.6
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• pp.506-509
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• 2005

This paper presents the improved burn-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved by the burn-in process. Reliability Problem is very significant in the MCP which includes over two chips in a package because the failure of one SRAM chip has a large influence on the yield and quality of the other chips such as Flash Memory, DRAM, etc. Therefore the quality of SRAM must be guaranteed. To improve the qualify of SRAM, we applied the improved wafer level burn-in process using multi cell selection method in addition to the previously used methods and it is found to be effective in detecting particular failures. Finally, with the composition of some kinds of methods, we achieved the high quality of SRAM in MCP.

• Journal of the Korean Society for Nondestructive Testing
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• v.21 no.6
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• pp.598-606
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• 2001

Recently, semiconductor packages trend to be thinner, which makes difficult to detect defects therein. A preconditioning test is generally performed to evaluate the reliability of semiconductor packages. The test procedure includes two scanning acoustic microscope (SAM) tests at the beginning and end of the entire test, in order to help detect physical defects such as delaminations and package cracks. In particular, of primary concern are package cracks and delaminations caused by moisture absorbed under ambient conditions. This paper discusses the failure mechanism associated with the moisture absorbed and encapsulated in semiconductors, and the use SAM to detect failures such as tracks and delaminations grown during the preconditioning test.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2007.04a
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• pp.67-79
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• 2007