• Journal of Power Electronics
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• v.12 no.5
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• pp.689-698
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• 2012

This paper investigates the effects of applying different input current waveshapes on the performance of a continuous-conduction-mode (CCM) power-factor-correction (PFC) boost pre-regulator. It is found that the output voltage ripple of the pre-regulator can be reduced if the input current is modified to include controlled amount of higher order harmonics. This finding allows us to balance the performance of output regulation and the harmonic current emission when coming to the design of the pre-regulator. An experimental PFC boost pre-regulator prototype is constructed to verify the analysis and show the benefit of the pre-regulator operating with input current containing higher order harmonics.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.173-178
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• 1993

In this paper, we present an algorithmic technique for determining a feedback compensator which will stabilize the interval dynamic system, specifically, the robust regulator design for interval plants. The approach taken here is to allow the system parameters to live within prescribed intervals then design a dynamic feedback compensator which guarantees closed-loop system stable. The main contribution of this paper is the idea of introducing a "simplified Kharitonov's result" for low order polynomials to search for suitable compensator parameters in the compensator parameter space to make the uncertain syste robust. We also design the robust regulator which will D-stabilize (have the closed-loop poles in the left sector only) the dynamic interval system while having good performance. The nuerical examples are given to show the substantially improved robustness which results from our approach. approach.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.8
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• pp.64-73
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• 1994

In this paper we present an algorithmic technique for determining a feedback compensator which will stabilize the interval dynamic system specifically the robust regulator design for interval plants. The approach taken here is to allow the system parameters to live within prescribed intervals then design a dynamic feedback compensator which guarantees closed-loop system stable. The main contribution of this paper is the idea of introducting a "simplified Kharitonov`s results" for low order polynomials to search for suitable compensator parameters in the compensator parammeter space to make the uncertain system robust. We also design the robust regulator which will $D_{\phi}$ -stabilize (have the closed-loop poles in the left sector only) the dynamic interval system while having good performance. the numerical examples are given to show the substantially improved robustness which results from our approach.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.845-846
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• 2008

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.2
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• pp.269-273
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• 2009

A voltage regulator can be used to reduce the effect of the power-supply noise on the control voltage of the VCO. An accurate analysis of the voltage regulator circuit is needed for the optimal design of the voltage regulator. This paper clarifies an inaccuracy in a recent paper on the replica-compensated regulator far supply-regulated PLLs: neglect of MOSFET parasitic capacitances. As a consequence, an improved analytical model is derived for the replica-compensated voltage regulator. The derived model is verified through circuit simulation. The voltage regulator has been fabricated in a standard $0.18{\mu}m$ 1P6M CMOS technology. The chip area is $1mm^2$.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.253-256
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• 1997

This paper describes a novel design method for compensating field time-constant of micro-synchronous machine so that its terminal flux can show the same characteristics as large-scale synchronous machine's. In addition to it, the suggested design method can determine the field time-constant regulator's parameters considered the nonlinearities of micro-synchronous machine such as saturation and loading effect. This method applied to 5kVA micro-synchronous machine, and the digital time-constant regulator with digital AVR were designed such that the short field time-constant, $T_{do}'=1.12\;sec$, can take on the large-scale synchronous machine time constant, $T_{do}'=1.47\;sec$. After determining the parameters of controllers, the real time digital time-constant regulator and digital AVR algorithm were implemented by using the PC with Penumum processor, and the usefulness of suggested real time digital time-constant regulator was verified by observing its good performance on the excitation of micro-synchronous machine.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.17 no.11
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• pp.1093-1101
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• 2007

This study presents the design improvement process for door module. Its objective evades the resonance generated at module plate due to the operation of window regulator motor. For this study, the design improvement process is composed of experimental methods having three steps. First step is modal analysis at door assembly status for acquisition of dynamic characteristics which are modal frequency and damping. Second step is a vibration experiment to get the test mode considered an efficiency of window regulator motor. Last step is a vibration measurement by the form of $6{\times}6$ array on module plate. A vibration measurement of $6{\times}6$ array form can be got to three analysis results which are a transfer path of vibration using cross correlation function, a vibration map using OA level and a contribution by frequency band using coherent output power spectrum on module plate. These results are applied to SDM(structural dynamic modification) for design improvement to get around the resonance on module plate by the excitation of window regulator motor.

• International Journal of Aeronautical and Space Sciences
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• v.17 no.3
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• pp.401-408
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• 2016

During daylight, the solar array of low earth orbit satellites harvests electrical power to operate satellites. The power conversion of the solar array is carried out by control of the operation point using the solar array regulator when the solar array faces the sunlight. Thus, the design of the solar array should comply with not only the power requirement of satellite system but also the input voltage requirement of the solar array regulator. In this paper, the design requirements of the solar array for low earth orbit satellites are defined, and the means of satisfying these requirements are described. In addition, the architecture of a multi-distributed interface is suggested to maximize the power harvested from a solar array having high temperature deviation between each panel. The power analysis in this paper shows the optimal number of multi-distributed interfaces with a converter.

• Journal of the Korean Society for Aviation and Aeronautics
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• v.17 no.1
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• pp.24-28
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• 2009

The reliability assessment is performed for Pressure Control Regulator of Aircraft Fuel System using reliability procedure which consists of the reliability analysis and the Failure Modes and Effects Analysis(FMEA). The target reliability as MTBF(Mean Time Between Failure) is set to 5000hr. During the reliability analysis process, the system is categorized by Work Breakdown Structure(WBS) up to level 3, and a reliability structure is defined by schematics of the system. Since the components and parts that have been collected through EPRD/NPRD. The predicted reliability to meet mission requirements and operating conditions is estimated as 4375.9hr. To accomplish the target reliability, the components and parts with high RPN have been identified and changed by analyzing the potential failure modes and effects. By changing the configuration design of components and parts with high-risk, the design is satisfied target reliability.

• Journal of Applied Reliability
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• v.7 no.1
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• pp.1-11
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• 2007

This paper presents a derating design approach for reliability improvement of a regulator IC. The IC is usually used in SMPS. The main failure mechanism of interest is voltage drop due to the package delamination mainly caused by two stresses, i.e. temperature and current. The lifetime under stresses is modeled as a function of stresses and time using accelerating life testings. Quantitative and qualitative variation in lifetime according to stress variations are investigated using the modeled lifetime. Stress levels would be determined to achieve required reliability levels in the aspect of derating design for reliability.