• Journal of the Society of Naval Architects of Korea
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• v.43 no.1 s.145
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• pp.68-74
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• 2006

The welding distortion of a hull structure in the shipbuilding industry is inevitable at each assembly stage. This geometric inaccuracy caused by the welding distortion tends to preclude the introduction of automation and mechanization and needs the additional man-hours for the adjusting work at the following assembly stage. To overcome this problem, a distortion control method should be applied. For this purpose, it is necessary to develop an accurate prediction method which can explicitly account for the influence of various factors on the welding distortion. The validity of the prediction method must be also clarified through experiments. For the purpose of reducing the weld-induced bending deflection, this paper proposes the mechanical tensioning method (MTM) as the optimum distortion control method. The validity of this method has been substantiated by a number of numerical simulations and actual measurements.

• Agribusiness and Information Management
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• v.1 no.2
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• pp.43-60
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• 2009

To improve the performance of wide-issue superscalar processors, it is essential to increase the width of instruction fetch and the issue rate. Removal of control hazard has been put forward as a significant new source of instruction-level parallelism for superscalar processors and the conditional branch prediction is an important technique for improving processor performance. Branch mispredictions, however, waste a large number of cycles, inhibit out-of-order execution, and waste electric power on mis-speculated instructions. Hence, the branch predictor with higher accuracy is necessary for good processor performance. In global-history-based predictors like gshare and GAg, many mispredictions come from commit update of the branch history. Some works on this subject have discussed the need for speculative update of the history and recovery mechanisms for branch mispredictions. In this paper, we present a new mechanism for recovering the branch history after a misprediction. The proposed mechanism adds an age_counter to the original predictor and doubles the size of the branch history register. The age_counter counts the number of outstanding branches and uses it to recover the branch history register. Simulation results on the SimpleScalar 3.0/PISA tool set and the SPECINT95 benchmarks show that gshare and GAg with the proposed recovery mechanism improved the average prediction accuracy by 2.14% and 9.21%, respectively and the average IPC by 8.75% and 18.08%, respectively over the original predictor.

• ETRI Journal
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• v.19 no.3
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• pp.186-201
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• 1997

In this paper, a home location register (HLR) for CDMA mobile communication system (CMS) is introduced. It stores the mobile station (MS) subscribers locations and supplementary service information. Call processing procedures for HLR are developed to receive and store subscriber's location coming from mobile exchange (MX) during the location registration, and to transfer subscriber's location and supplementary service information to the MX during the mobile-terminated call setup. For fast call processing by increasing database access speed, a memory-resident database management system is devised. For Easy and secure HLR operation, administration and maintenance functions and overload control mechanisms are implemented. Designed HLR hardware platform is expandable and flexible enough to reallocated software blocks to any subsystems within the platform. It is configurable according to the size of subscribers. An authentication center (AC) is developed on the same platform. It screens the qualified MS from the unqualified. The calls to and from the unqualified MS are rejected in CMS. To authenticate the MS, the AC generates a new authentication parameter called "AUTHR" using shared secret data (SSD) and compared it with the other AUTHR received from the MS. The MC also generates and stores seed keys called "A-keys" which are used to generate SSDs. The HLR requirements, the AC requirements, software architecture, hardware platform, and test results are discussed.

• The Journal of Information Technology
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• v.5 no.4
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• pp.165-171
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• 2002

We propose Dynamic Circle Location Register (DCLR) scheme where each visiting location register (VLR) has a given fixed circle registration area around itself and has IDs of other VLRs in this circle area. Whenever a terminal moves to another registration area (RA), system computes whether the terminal is located in the current DCLR area and sends the recent location information of terminal to the old or new DCLR according to computing results. Also, according to change DCLR circle dynamically, we can track terminal location by querying DCLR of the current terminal when a call originates. The our scheme solves the HLR bottleneck due to the terminals frequent RA crossings and distributes the registration traffic to each of the local signaling transfer point (LSTP) area in wireless communications (WC)

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.1
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• pp.30-38
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• 1995

In this paper, we propose an efficient architecture for motion estimation processor which performs one of essential functions in moving picture coding algorithms. Simple control mechanism of data flow in register array which stores pixel data, parallel processing of pixel data and pipelining scheme in arithmetic umit allow this architecture to process a 352*288 pixel image at the frame rate of 30fs, which is compatable with CCITT standard H.261.

• International Journal of Railway
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• v.2 no.1
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• pp.18-21
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• 2009

The basis of modem risk-based safety management is to focus on what might happen and ensure it is designed out of the system by robust hazard identification and risk analysis. However, in the real world things go wrong and it is essential to be prepared for the worst so that the response can minimise harm and loss of property and damage to the environment. Whilst some hazard mitigation measures are aimed at preventing incidents, others are venting escalation. The results of the tests concluded that the most effective means by the control room, both with and without, local station staff assistance using directive public address announcements and CCTV surveillance.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.376-379
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• 2001

In this paper, I design the control chip that controls inner test sequence of Logic Tester to test chip. Logic tester has the thirteen inner instructions to control test sequence in test. And these instructions are saved in memory with test pattern data. Control chip generates address and control signal such as read, write signal of memory. Before testing, necessary data such as start address, end address, etc. are written to inner register of control chip. When test started, control chip receives the instruction in start address and executes, and generates address and control signals to access tester' inner memory. So whole test sequence is controlled by making the address and control signal in tester's inner memory. Control chip designs instruction's execution blocks, respectively. So if inner instruction is added from now on, a revision is easy. The control chip will be made using FPGA of Xilinx Co. in future.

• Journal of Advanced Marine Engineering and Technology
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• v.41 no.4
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• pp.362-367
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• 2017

This study was conducted to compare the particulate removal efficiency of the developed diesel particulate filter using various measurement methods in a high-speed marine diesel engine. A four-stroke mechanical marine diesel engine is used for the test, which has a maximum output of 403 kW and is coupled to an AC dynamometer to control engine speed and load. The test was conducted based on four steady-state engine operating conditions of E3 engine test cycle for the measurement of PM and soot removal efficiency using partial dilution method considered as gravimetric method and filter smoke number method as light absorption method, respectively. As a result of the removal efficiency measurement according to the application of diesel particulate filter, particulate matter was reduced from 76% to 91% and the soot was reduced by more than 90% while meeting the permissible engine back pressure. From these results, the applicability of diesel particulate filter adopted in high-speed marine diesel engines could be confirmed. In addition, based on the result that the particulate removal efficiency varies with different measurement methods, the necessity of unification of these methods could be identified.

• Journal of the Korean Society of Marine Environment & Safety
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• v.29 no.6
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• pp.666-671
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• 2023

As international environmental regulations on ship emissions are gradually strengthened, interest in electric propulsion and hybrid propulsion ships is increasing, and various solutions are being developed and applied to these ships, especially stabilization of the power system and system efficiency. The direct current distribution system is being applied as a way to increase the power. In addition, verification and testing of safety and performance of marine DC distribution systems is required. As a result of establishing a DC distribution test bed, verifying the performance of the DC distribution (variable speed power generation) system, and analyzing fuel consumption, this study applied a variable speed power generation system that is applied to DC power distribution for ships, and converted the power output from the generator into a rectifier. A system was developed to convert direct current power to connect to the system and monitor and control these devices. Through tests using this DC distribution system, the maximum voltage was 751.5V and the minimum voltage was 731.4V, and the voltage fluctuation rate was 2.7%, confirming that the voltage is stably supplied within 3%, and a variable speed power generation system was installed according to load fluctuations. When applied, it was confirmed through testing that fuel consumption could be reduced by more than 20% depending on the section compared to the existing constant speed power generation system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2850-2861
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• 1996

This paper describes the design of AATM switch LIS of shared buffer type with linked-list architecture to control memory access. The proposed switch LSI consists of the buffer memory, controller and FIFO memory blocks and two special circuits to avoid the cell blocking. One of the special circuit is a new address control scheme with linked-list architecture which maintains the address of buffer memory serially ordered from write address to read address. All of the address is linked as chain is operated like a FIFO. The other is slip-flag register it will be hold the address chain when readaddress missed the reading of data. The circuits control the buffer memory efficiently and reduce the cell loss rate. As a result the designed chip operates at 33ns and occupied on 2.7*2.8mm$^{2}$ using 0.8.mu.m CMOS technology.