• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.281-286
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• 2007

In this paper, sub-circuits for 24 GHz phase locked 100ps(PLLs) using $0.5{\mu}m$ SiGe HBT are presented. They are 24 Ghz voltage controlled oscillator(VCO), 24 GHz to 12 GHz regenerative frequency divider(RFD) and 12 GHz to 1.5 GHz static frequency divider. $0.5{\mu}m$ SiGe HBT technology, which offers transistors with 90 GHz fMAX and 3 aluminum metal layers, is employed. The 24 GHz VCO employed series feedback topology for high frequency operation and showed -1.8 to -3.8 dBm output power within tuning range from 23.2 GHz to 26 GHz. The 24 GHz to 12 GHz RFD, based on Gilbert cell mixer, showed 1.2 GHz bandwidth around 24 GHz under 2 dBm input and consumes 44 mA from 3 V power supply including I/O buffers for measurement. ECL based static divider operated up to 12.5 GHz while generating divide by 8 output frequency. The static divider drains 22 mA from 3 V power supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.10
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• pp.1107-1113
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• 2009

In this paper, the design and implementation of K-Band frequency dividers using 130 nm CMOS process are presented. A Miller frequency divider is presented, which realizes a division range from 20 to 25 GHz with 7.2 mW power consumption from 1.2 V supply. The layout size of the core circuit is about $315{\times}246\;um^2$. In addition, a CML frequency divider which divides the output signal of the Miller frequency divider is also presented, which realizes a division range from 8.5 to 13 GHz with 5.7 mW power consumption. The layout size of the CML core is about $91{\times}98\;um^2$. Cascading the Miller and CML frequency dividers, we confirmed the divide-by-4 operation for the input signal from 20 to 25 GHz.