• 한국전기전자재료학회논문지
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• 제23권2호
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• pp.89-92
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• 2010

A bolometer sensor used in an infrared thermal imaging system has many advantages on the process because it does not need a separate cooling system and its manufacturing is easy. However the sensitivity of the bolometer is low and the fixed pattern noise(FPN) is large, because the bolometer sensor is made by micro electro mechanical systems (MEMS). These problems can be fixed-by using the high performance readout integrated circuit(ROIC) with noise reduction techniques. In this paper, we propose differential delta sampling circuit to remove the mismatch noise of ROIC itself, the FPN of the bolometer. And for reduction of FPN noise, the reference signal compensation circuit which compensate the reference signal by using on-resistance of MOS transistor was proposed.

• 센서학회지
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• 제18권4호
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• pp.280-285
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• 2009

In this paper, we designed a 2-stage CMOS operational amplifier with temperature compensation function using 2-poly 4-metal 0.35 $\mu$m standard CMOS technology. Using two bias circuits, the positive temperature coefficient(PTC) and the negative temperature coefficient(NTC) of the bias circuit are canceled out each other. When reference current circuit is simulated that it has a temperature coefficient of -150 ppm/$^{\circ}C$ with a temperature change from 0 $^{\circ}C$ to 120 $^{\circ}C$. Also the proposed circuit has a temperature coefficient of -0.011 dB/$^{\circ}C$ of DC open loop gain with the same temperature range.

• Journal of Power Electronics
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• 제10권4호
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• pp.412-418
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• 2010

This paper proposes a new algorithm to generate a reference signal for an active power filter using a sliding-window FFT operation to improve the steady-state performance of the active power filter. In the proposed algorithm the sliding-window FFT operation is applied to the load current to generate the reference value for the compensating current. The magnitude and phase-angle for each order of harmonics are respectively averaged for 14 periods. Furthermore, the phase-angle delay for each order of harmonics passing through the controller is corrected in advance to improve the compensation performance. The steady-state and transient performance of the proposed algorithm was verified through computer simulations and experimental work with a hardware prototype. A single-phase active power filter with the proposed algorithm can offer a reduction in THD from 75% to 4% when it is applied to a non-linear load composed of a diode bridge and a RC circuit. The active power filter with the proposed reference generation method shows accurate harmonic compensation performance compared with previously developed methods, in which the THD of source current is higher than 5%.

• 전기학회논문지
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• 제62권10호
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• pp.1487-1493
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• 2013

A new simple control method for active power filter, which can realize the complete compensation of harmonics is proposed. In the proposed scheme, a model-based digital current control strategy is presented. The proposed control system is designed and implemented in a form referred to as internal model control structure. This method provides a convenient way for parameterizing the controller in term of the nominal system model, including time-delays. As a result, the resulting controller parameters are directly set based on the power circuit parameters, which make tuning of the controllers straightforward task. In the proposed control algorithm, overshoots and oscillations due to the computation time delay is prevented by explicit incorporating of the delay in the controller transfer function. In addition, a new compensating current reference generator employing resonance model implemented by a DSP(Digital Signal Processor) is introduced. Resonance model has an infinite gain at resonant frequency, and it exhibits a band-pass filter. Consequently, the difference between the instantaneous load current and the output of this model is the current reference signal for the harmonic compensation.

• Journal of Power Electronics
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• 제2권1호
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• pp.55-66
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• 2002

A new on-line dead-time compensation method for a permanent magnet (PM) synchronous motor drive is proposed. Using a simple disturbance observer without any additional circuit and off-line experimental measurement, disturbance voltages in the synchronous reference dq frame caused by the dead time and non-ideal switching characteristics of power devices are estimated in an on-line manner and fed to voltage references in order to compensate the dead-time effects. The proposed method is applied to a PM synchronous motor drive system and implemented by using software of a digital signal processor (DSP) TMS320C31. Simulations and experiments are carried out for this system and the results well demonstrate the effectiveness of the proposed method.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.580-583
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• 2002

An improved MPPT converter with current compensation method for small-scaled PV-applications is presented in this paper. The proposed method implements maximum power point tracking (MPPT) by variable reference current which is continuously changed during one sampling period. Therefore, the power transferred to the load is increased above $9\%$ by the proposed MPPT converter with current compensation method. As a result, the utilization efficiency of Photovoltaic (PV)-panel can be increased. In addition, as it doesn't use digital signal processor (DSP), this MPPT method has the merits of both a cost efficiency and a simple control circuit design. Therefore, it is considered that the proposed MPPT method is proper to low power, low cost PV-applications. The concept and control principles of the proposed MPPT method are explained in detail and its validity of the proposed method is verified through several simulated results.

• 전자공학회논문지T
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• 제35T권1호
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• pp.48-58
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• 1998

본 논문은 센서에서 수반되는 기생용량과 온도 드리프트 및 누설전류의 영향을 경감하기 위한 C-V변환회로 및 C-V변환회로에 관한 실험결과를 제시하고, 또한 논문에서 제안한 센싱 주파수를 기준주파수로 나누어줌으로써 상기 영향들을 줄일 수 있는 새로운 인터페이스 회로를 제시한다 이 회로는 용량비의 출력신호를 디지털 방식으로 16진수로 계수 함으로써 신호의 전송이나 컴퓨터 처리가 쉬울 뿐 아니라 비트수의 증가에 따라 분해 능을 향상시킬 수 있는 이점도 있다. 시작한 인터페이스 회로의 C-V 및 C-F 변환회로에서 전원전압 4.0V, 피이드백 커패시턴스10pF, 압력 0∼10 KPa범위에서 감도는 각각 28 ㎷/㎪·V, -6.6 ㎐/㎩로서 양호하였고, 온도 드리프트 특성은 0.051 %F.S./℃ 및 0.078 %F.S./℃로서 크게 개선되었다.

• Journal of Power Electronics
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• 제13권1호
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• pp.51-58
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• 2013

This paper proposes the power conversion mechanism of a bailer-charge-transfer zero-current-switching (CT-ZCS) circuit. The operation modes are analyzed and researched using state trajectory equations. The topology of CT-ZCS based on soft-switching inverters offers some merits such as: tracking the input reference signal dynamically, bearing load shock and short circuit, multiplying inverter N+1 redundancy parallel, coordinating power balance for easy control, and soft-switching commutation for high efficiency and large capacity. These advantages are distinctive from conventional inverter topologies and are especially demanded in AC drives: new energy generation and grid, distributed generation systems, switching power amplifier, active power filter, and reactive power compensation and so on. Prototype is manufactured and experiment results show the feasibility and dynamic voltage-tracking characteristics of the topology.

• 전력전자학회논문지
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• 제8권2호
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• pp.143-150
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• 2003

본 논문에서는 소규모 태양광 발전시스템에 적합한 전류보상기법을 갖는 개선된 최대전력 점 추적시스템을 제안하고자 한다. 제안된 전류보상기법을 갖는 개선된 최대전력 점 추적시스템은 한 샘플링 주기 동안에도 매 수위칭 주기마다 가변 레퍼런스 전류를 생성하여 최대전력 점 추적(MPPT)을 수행하는 방식이다. 이로 인해 세안한 방식은 기존 방식보다도 부하측으로 전달되는 출력전력이 약 9%정도 증가되었다. 그 결과 태양광 패널의 이용률이 상당히 증가될 것으로 사료된다. 또한 제안한 방식은 DSP를 사용하지 않기 때문에 제어회로가 단순하여 회로구성이 용이할 뿐만 아니라 저 비용의 특징을 가지고 있다. 그러므로 제안한 방식은 저 전적, 저 비용의 소규모 태양광 시스템에 적합한 방식으로 사려된다. 본 논문에 제안한 개선된 최대전력 점 추적시스템의 개념 및 제어원리가 자세히 설명되고 있고 또한 제안한 방식의 타당성을 검증하기 위해 시뮬레이션을 수행하였다.

• 한국콘텐츠학회논문지
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• 제6권3호
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• pp.38-45
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• 2006

본 논문은 LCD driver IC의 전송선 당 데이터 전송률을 2배로 하기 위한 이중 저전압 차동신호 전송 (DLVDS) 회로를 제안한다. 제안된 회로에서는 2-비트 데이터를 하나의 송신기에서 입력 받고, 2-비트 데이터를 듀얼레벨을 갖는 차동신호로 전송한다. 따라서 기존의 저전압 차동신호 전송기법(LVDS)의 특징을 유지하면서 2-비트 데이터를 2개의 전송선을 통하여 전송할 수 있다. 제안된 송신기는 전류원 피드백 회로를 이용하여 출력의 공통모드 바이어스 흔들림을 보상했다. 그리하여 기존의 회로의 입력 바이어스와 기준 바이어스 전압 차이로 출력의 공통모드 바이어스 흔들림이 발생하는 문제가 해결되었다. 수신기에서는 디코드 회로를 통해 원래의 2-비트 입력 데이터를 복원할 수 있다. 제안된 회로는 $0.25{\mu}m$ CMOS 공정으로 설계하였고, 시뮬레이션 결과 1-Gbps/2-line의 전송률을 갖고, 2.5V의 전원에서 35-mW의 전력소모를 나타냈다.