• KIISE Transactions on Computing Practices
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• v.23 no.2
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• pp.110-115
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• 2017

We propose a new indoor positioning algorithm named Cut-off algorithm. This algorithm cuts off candidates of beacons and reference points in advance, before looking for K neighbor reference points which are guessed to be closest to the user's actual location. The algorithm consists of two phases: off-line phase, and on-line phase. In the off-line phase, RSSI and UUID data from beacons are gathered at reference points placed in the indoor environment, and construct a fingerprint map of the data. In the on-line phase, the map is reduced to a smaller one according to the RSSI data of beacons received from the user's device. The nearest K reference points are selected using the reduced map, which are used for estimating user's location. In both phases, relative ranks of the peak signals received from each beacon are used, which smoothen the fluctuations of the signals. The algorithm is shown to be more efficient in terms of accuracy and estimating time.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• Journal of Positioning, Navigation, and Timing
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• v.12 no.4
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• pp.359-367
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• 2023

In order to ensure the high-integrity of reference stations of satellite navigation system, cycle slip should be precisely monitored and compensated. In this paper, we proposed a cycle slip algorithm for the integrity monitoring of the reference stations. Unlike the legacy method using the Melbourne-Wübbena (MW) combination and ionosphere combination, the proposed algorithm is based on ionosphere combination only, which uses high precision carrier phase observations without pseudorange observations. Two independent and complementary ionosphere combinations, Ionospheric Negative (IN) and Ionospheric Positive (IP), were adopted to avoid insensitive cycle slip pairs. In addition, a second-order time difference was applied to the IN and IP combinations to minimize the influence of ionospheric and tropospheric delay even under severe atmosphere conditions. Then, the cycle slip was detected by the thresholds determined based on error propagation rules, and the cycle slip was identified through weighted least square method. The performance of the proposed cycle slip algorithm was validated with the 1 Hz dual-frequency carrier phase data collected under the difference levels of ionospheric activities. For this experiment, 15 insensitive cycle slip pairs were intentionally inserted into the raw carrier phase observations, which is difficult to be detected with the traditional cycle slip approach. The results indicate that the proposed approach can successfully detect and compensate all of the inserted cycle slip pairs regardless of ionospheric activity. As a consequence, the proposed cycle slip algorithm is confirmed to be suitable for the reference station where real time high-integrity monitoring is crucial.

• Journal of Electrical Engineering and Technology
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• v.8 no.3
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• pp.507-515
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• 2013

This paper proposes a compensation method for the $2^{nd}$-order harmonic of single-phase grid-connected wind power generation systems. Theoretically, a single-phase grid-connected inverter system has no choice but to cause the $2^{nd}$-order harmonic to DC-link voltage. The reference active current is affected by the DC-link voltage. The output current from the reference active current is distorted by the $1^{st}$ and $3^{rd}$-order harmonic. The proposed method can compensate, conveniently, the reference active current with the $2^{nd}$-order harmonic. To reduce the $2^{nd}$-order ripple in the reference active current, proposed method takes a PR controller as a feed-forward compensator. PR controllers can implement selective harmonic compensation without excessive computational requirements; the use of these controllers simplifies the method. Both the simulation and experimental results agree well with the theoretical analysis.

• Journal of Positioning, Navigation, and Timing
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• v.11 no.2
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• pp.83-89
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• 2022

For precise GNSS applications, the antenna phase center correction (PCC) is absolutely required. The PCC magnitude can reach the centimeter level with the antenna structure. In the present study, we first investigate the phase center offset (PCO) and phase center variation (PCO) of three different antenna models in two different reference frames, IGS08/igs08.atx and IGS14/igs14.atx. Clear L1 and L2 PCO differences were found between IGS08 and IGS14. In addition, the PCV showed characteristics that is dependent upon the signal direction (azimuth and elevation angle). The remarkable thing is that the changes of a Dorne Margolin choke-ring antenna model (AOAD/MT DOME) was very small in two reference frames. In order to analyze changes in positions according to different reference systems, GNSS data obtained from DAEJ, SUWN, and TSKB stations were processed by the precise point positioning (PPP) method. We suggest that an antenna PCO/PCV can affect the precise GNSS positioning on the order of several millimeters in two different reference frames.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.54 no.7
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• pp.335-342
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• 2005

This paper presents a circuit to generate the current reference signal for single-phase harmonic elemination systems. Some of conventional methods for the current reference signal generation based on neural network algorithms. It requires complex circuitry to implement. the simplest method is to use analog filters. but it is difficult to obtain good current reference signals. So, we propose the harmonic detection circuit using GIC(Generalized Impedance Converter) for the purpose of low cost ,simple circuitry and high performance, Simulation and experimental results verify that the proposed circuit has better harmonic detection performance than conventional circuit.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.51 no.4
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• pp.219-221
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• 2002

This paper presents an electric scooter development using blushless DC motor. In recent scooters was to develop for sport leisure and short transportation. Most of scooter are used petroleum gas. This gas scooter has disadvantage to pollute the air. Some of scooters have developed by DC motor which require a brush. However brushless motors have higher maximum speed and greater capacity, save maintenance labour and produce less noise. There is also greater freedom in planing the usage of brushless motors. In this paper we develop an electric scooter driving BLDC motor for design smart system and control speed of scooter with current reference signal to apply voltage to motor by means of three phase inverter. Using accelerator device we generate current reference to control speed and send the current to a MICOM by A/D converter. This MICOM produces the voltage signal and hall sensors signal and PWM controller drive three phase inverter to minimize error between the reference and an actual current.

• Journal of electromagnetic engineering and science
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• v.17 no.3
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• pp.138-146
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• 2017

A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

• Journal of the Optical Society of Korea
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• v.13 no.2
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• pp.245-250
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• 2009

We propose a digital holographic interference analysis method based on a 2-frame phase-shifting technique for measuring an optical mirror surface. The technique using 2-frame phase-shifting digital interferometry is more efficient than multi-frame phase-shifting techniques because the 2-frame method has the advantage of a reduced number of interferograms, and then takes less time to acquire the wanted topography information from interferograms. In this measurement system, 2-frame phase-shifting digital interferograms are acquired by moving the reference flat mirror surface, which is attached to a piezoelectric transducer, with phase step of 0 or $\pi$/2 in the reference beam path. The measurements are recorded on a CCD detector. The optical interferometry is designed on the basis of polarization characteristics of a polarizing beam splitter. Therefore the noise from outside turbulence can be decreased. The proposed 2-frame algorithm uses the relative phase difference of the neighbor pixels. The experiment has been carried out on an optical mirror which flatness is less than $\lambda$/4. The measurement of the optical mirror surface topography using 2-frame phase-shifting interferometry shows that the peak-to-peak value is calculated to be about $0.1779{\mu}m$, the root-mean-square value is about $0.034{\mu}m$. Thus, the proposed method is expected to be used in nondestructive testing of optical components.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.103-105
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• 2008

In grid-interconnection system, a fast, robust and precise phase angle detector is most important to grid synchronization and the active power control. The phase angle can be easily estimated by synchronous dq PLL system. On the other hand under unbalanced voltage condition, synchronous dq PLL system has problem that harmonics occur to phase angle or magnitude of grid voltage because of the effect of the negative sequence components. So, To eliminate the negative sequence components, the PLL method using APF (All Pass Filter) in a stationery reference frame to extract positive sequence components under unbalanced voltage condition is researched. In this paper, we propose a new PLL method with decoupling network using APF in a synchronous reference frame to extract the positive sequence components of the grid voltage under unbalanced grid. The cut-off frequency of APF in a synchronous reference frame can be set to twice of the fundamental frequency comparing with that of APF in a stationery reference frame which is the fundamental frequency. The proposed PLL strategy can detect the phase angle quickly and accurately under unbalanced gird voltages. Simulation and experimental results are presented to verify the proposed strategy under different kind of voltage dips.