• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 정기총회 및 추계학술대회 논문집 학회본부
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• pp.91-93
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• 1993

This paper introduced an advanced PWM method to drive a variable speed AC motor. With this technique, a switching pattern is determined to minimize the error between a reference signal and feedback signal. In addition to its simplicity of implementation, the proposed technique has the advantage of control led constant voltage per frequency operation.

• Journal of information and communication convergence engineering
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• 제10권2호
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 B
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• pp.984-985
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• 2006

This paper presents control algorithms for unified active power filter. The algorithm is based in the performance function. The performance function is defined, and the compensation voltage reference is calculated for harmonics voltage and the compensation current reference is calculated for power factor. The proposed control algorithm can be applied to 3-phase 3-wire system and has a superior compensation characteristics for both harmonic current sources and harmonic voltage sources.

• 전기전자학회논문지
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• 제24권3호
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• pp.867-876
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• 2020

본 논문에서는 3레벨 인버터로 구동되는 IPMSM의 고주파 주입 센서리스 운전에서 중성점 전압 리플 저감을 제안한다. 고주파 전압 주입 기반의 센서리스 제어는 IPMSM의 저속 영역에서 일반적으로 사용하는 센서리스 제어 기법이다. 고주파 전압 주입을 이용한 IPMSM의 센서리스 제어 과정에서 중성점에서의 전압 리플이 증가하는 문제가 발생한다. 중성점에서의 큰 전압 리플은 출력 전류를 왜곡시킬 뿐만 아니라 직류단 커패시터의 수명을 단축시키므로 저감되어야 한다. 본 논문에서 제안하는 기법은 지령 전압에 적절한 값을 보상하여 중성점 전압 리플을 저감하며, 보상값은 지령 전압과 전류를 이용하여 간단히 계산한다. 제안하는 중성점 전압 리플 저감 기법의 타당성은 시뮬레이션을 통해 검증한다.

• Journal of Power Electronics
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• 제16권4호
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• pp.1551-1564
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• 2016

The high penetration level of inverter-based distributed generation (DG) power plants is challenging the low-voltage ride-through requirements, especially under unbalanced voltage sags. Recently, a flexible injection of both positive- (PS) and negative-sequence (NS) reactive currents has been suggested for the next generation of grid codes. This can enhance the ancillary services for voltage support at the point of common coupling (PCC). In light of this, considering distant grid faults that occur in a mainly inductive grid, this paper proposes a complete voltage support control scheme for the interface inverters of medium or high-rated DG power plants. The first contribution is the development of a reactive current reference generator combining PS and NS, with a feature to increase the PS voltage and simultaneously decrease the NS voltage, to mitigate voltage imbalance. The second contribution is the design of a voltage support control loop with two flexible PCC voltage set points, which can ensure continuous operation within the limits required in grid codes. In addition, a current saturation strategy is also considered for deep voltage sags to avoid overcurrent protection. Finally, simulation and experimental results are presented to validate the effectiveness of the proposed control scheme.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제52권8호
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• pp.405-412
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• 2003

This paper presents a three-phase Line-Interactive uninterruptible power supply (UPS) system with series-parallel active power-line conditioning capabilities, using synchronous reference frame (SRF) based controller, which allows an effective power factor correction, source harmonic voltage compensation, load harmonic current suppression, and output voltage regulation. The three-phase UPS system consists of two active power compensator topologies. One is a series active compensator, which works as a voltage source in phase with the source voltage to have the sinusoidal source current and high power factor under the deviation and distortion of the source voltage. The other is a parallel active compensator which works as a conventional sinusoidal voltage source in phase with the source voltage, providing to the load a regulated and sinusoidal voltage with low THD (total harmonic distortion). The control algorithm using SRF method and the active power flow through the Line-interactive UPS systems are described and studied. The simulation and experimental results are depicted in this paper to show the effect of the proposed algorithm.

• Journal of Power Electronics
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• 제5권1호
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• pp.11-19
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• 2005

This paper describes the two control techniques to perform the sensorless vector control of a PMSM by injecting the high frequency voltage to the stator terminal. The first technique is the estimation algorithm of the initial rotor position. A PMSM possesses the saliency which produces the ellipse of the stator current when the high frequency voltage is injected into the motor terminal. The major axis angle of the current ellipse gives the rotor position information at a standstill. The second control technique is a sensorless control algorithm that injects the high frequency voltage to the stator terminal in order to estimate the rotor position and speed. The rotor position and speed for sensorless vector control is calculated by appropriate signal processing to extract the position information from the stator current at low speeds or standstill. The proposed sensorless algorithm using the double-band hysteresis controller exhibits excellent reference tracking and increased robustness. Experimental results are presented to verify the feasibility of the proposed control schemes. Speed, position estimation and vector control were carried out on the floating point processor TMS320VC33.

• 전기학회논문지
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• 제65권9호
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• pp.1479-1485
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• 2016

This paper presents DC voltage recovery time improvement method in DC link of High Voltage Direct Current (HVDC) with offshore wind farm. The wind farm should be satisfied Low Voltage Ride Through(LVRT) control strategy when grid faults occur. The LVRT control strategy indicates actions which have to be executed according to the voltage dip ratio and the fault duration. However, The LVRT control strategy makes between wind farm and power system through DC Link voltage when grid fault occurs. The de-loading scheme is one of the method to control the DC voltage. But de-loading scheme need to long DC voltage recovery time. Thus, this paper proposes an improved de-loading scheme and we analysis DC voltage and active power reference through a simulation.

• 한국철도학회논문집
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• 제12권5호
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• pp.694-699
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• 2009

교류 전기철도 급전시스템의 전압, 전류의 왜곡 및 전압 sag과 무효전력을 보상하기 위한 단상 UPQC의 동기좌표계를 이용한 제어 방법을 제안한다. 단상 UPQC의 동기좌표계를 이용한 제어를 통해 단상인버터 형태인 UPQC의 직렬보상기와 병렬보상기를 순시적으로 제어한다. 시뮬레이션을 통해 단상 UPQC를 이용하여 비선형 단상 부하인 차량으로 인해 급전시스템에 생길 수 있는 전압, 전류의 왜곡 및 전압 sag과 무효전력의 보상이 가능함을 증명하고, 단상 UPQC의 동기좌표계를 이용한 제어 방법이 타당함을 확인한다.

• 산업기술연구
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• 제28권B호
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• pp.167-174
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• 2008

In this paper, the analysis on type effect of inverter output voltage distortion on the control of an induction motor is discussed. The inverter output voltage is distorted differently from the reference voltage owing to the inverter nonlinear characteristic. The inverter nonlinear characteristic results from the voltage drop, the inherent characteristic of the power semiconductor, and the dead time for preventing the short circuit of the inverter leg. This characteristic distorts the inverter output voltage and then, causes the motor flux estimation error. Although this characteristics do not significantly effect in the general-purpose induction motor control, but significantly effect on the low-speed operation of high performance motor control such as the sensorless vector control.