• Journal of Advanced Navigation Technology
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• v.10 no.4
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• pp.299-305
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• 2006

DURUMI-II is developed into test bed airplane for the multi-purpose flight test. It satisfied the civil aeronautics law. DURUMI-II is equipped with Airborne System for acquiring of flight test data and can fly by oneself. In this paper, the redundancy of DURUMI-II control system is operated sequentially is explained. The divided control surface and the requiring program method for flight test are described. Also, it is described that the exact control input is applied using the new method. Finally, the results of flight test for new method are analyzed.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.122-130
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• 2013

The demand and the supply are increasing sharply in accordance with the growth of the Memory Semiconductor Industry. The Flash Memory above all is being utilized substantially in the Industry of smart phone, the tablet PC and the System on Chip (SoC). The Flash Memory is divided into the NOR-type Flash Memory and the NAND-type Flash Memory. A lot of study such as the Built-In Self Test (BIST), the Built-In Self Repair (BISR) and the Built-In Redundancy Analysis (BIRA), etc. has been progressed in the NOR-type fash Memory, the study for the Built-In Self Test of the NAND-type Flash Memory has not been progressed. At present, the pattern test of the NAND-type Flash Memory is being carried out using the outside test equipment of high price. The NAND-type Flash Memory is being depended on the outside equipment as there is no Built-In Self Test since the erasure of block unit, the reading and writing of page unit are possible in the NAND-type Flash Memory. The Built-In Self Test equipped with 2 kinds of finite state machine based structure is proposed, so as to carry out the pattern test without the outside pattern test equipment from the NAND-type Flash Memory which carried out the test dependant on the outside pattern test equipment of high price.

• The Journal of the Acoustical Society of Korea
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• v.20 no.1E
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• pp.14-19
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• 2001

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell installed in an Merged Memory with Logic(MML). It generates the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. It is possible to test the embedded SDRAM without external test pin. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by 0.25μm cell library and is verified by Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14n algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.787-797
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• 2008

In this paper, we propose a fast disparity estimation method considering temporal and spatial redundancy based on a dynamic programming for stereo matching. For the first step, the dynamic programming is performed to estimate disparity vectors with correlation between neighboring pixels in an image. Next, we efficiently compensate regions, which disparity vectors are not allocated, with neighboring disparity vectors assuming that disparity vectors in same object are quite similar. Moreover, in case of video sequence, we can decrease a complexity with temporal redundancy between neighboring frames. For performance comparison, we generate an intermediate-view image using the estimated disparity vector. Test results show that the proposed algorithm gives $0.8{\sim}2.4dB$-increased PSNR(peak signal to noise ratio) compared to a conventional block matching algorithm, and the proposed algorithm also gives approximately 0.1dB-increased PSNR and $48{\sim}68%$-lower complexity compared to the disparity estimation method based on general dynamic programming.

• Journal of KIISE:Information Networking
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• v.31 no.1
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• pp.1-10
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• 2004

This study discusses Application-layer FEC using erasure codes. Because of the simple decoding process, erasure codes are used effectively in Application-layer FEC to deal with Packet-level errors. The large number of parity packets makes the loss rate to be small, but causes the network congestion to be worse. Thus, a redundancy control algorithm that can adjust the number of parity packets depending on network conditions is necessary. In addition, it is natural that high-priority frames such as I frames should produce more parity packets than low-priority frames such as P and B frames. In this paper, we propose a redundancy control algorithm that can adjust the amount of redundancy depending on the network conditions and depending on data priority, and test the performance in simple links and congestion links.

• Journal of the Korean Geographical Society
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• v.45 no.6
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• pp.788-805
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• 2010

The present USN (Ubiquitous Sensor Networks) node deployment practices have many limitations in terms of positional connectivity. The aim of this research was to minimize a redundancy of USN route nodes, by integrating spatially weighted parameters such as visibility, proximity to cell center, road density, building density and cell overlapping ratio into a comprehensive GIS database. This spatially weighted approach made it possible to reduce the number of route nodes (11) required in the study site as compared to that of the grid network method (24). The field test for RSSI (Received Signal Strength Indicator) indicates that the spatially weighted deployment could comply with the quality assurance standard for node connectivity, and that reduced route nodes do not show a significant degree of signal fluctuation for different site conditions. This study demonstrated that the spatially weighted deployment can be used to minimize a redundancy of USN route nodes in a routine manner, and the quantitative evidence removing a redundancy of USN route nodes could be utilized as major tools to ensure the strong signal in the USN, that is frequently encountered in real applications.

• Journal of Advanced Marine Engineering and Technology
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• v.35 no.3
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• pp.341-347
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• 2011

The redundancy allocation problem (RAP) is a famous NP.complete problem that has beenstudied in the system reliability area of ships and airplanes. Recently meta-heuristic techniques have been applied in this topic, for example, genetic algorithms, simulated annealing and tabu search. In particular, tabu search (TS) has emerged as an efficient algorithmic approach for the series-parallel RAP. However, the quality of solutions found by TS depends on the initial solution. As a robust and efficient methodology for the series-parallel RAP, the hybrid metaheuristic (TSA) that is a interactive procedure between the TS and SA (simulated annealing) is developed in this paper. In the proposed algorithm, SA is used to find the diversified promising solutions so that TS can re-intensify search for the solutions obtained by the SA. We test the proposed TSA by the existing problems and compare it with the SA and TS algorithm. Computational results show that the TSA algorithm finds the global optimal solutions for all cases and outperforms the existing TS and SA in cases of 42 and 56 subsystems.

• Proceedings of the Korea Concrete Institute Conference
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• 1999.10a
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• pp.681-684
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• 1999

The development of external prestressing methods has been one of the major trends in the concrete bridge constructions over the past decades. One of the promising methods to enhance the flexural strength of a externally prestressed girder is to place the tendons with large eccentricities. The test results in this study showed that the external prestressing of a composite girder increased the range of the elastic behavior, reduced deflections, increased ultimate strength, and added to the redundancy by providing the multiple stress paths. This study was conducted on the concrete bridges reinforced by the continuous girders and the external prestressing.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1987.04a
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• pp.27-30
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• 1987

Some modification of laplacian pyramidal coding have been done and tested for a test image, From our studies, its apperar that 3-D redictor which exploits inter and intra plane redundancy simultaneously somewhat imporves the image quality, We also have tried to reduce the bit rate by only sending zeroth plane image values that correstpond to estimated dege points which can be obtained from the first plane For both cases the feedback of quantization errof in the previous plane has been in the reconstruction of each plane. Subjective and SNR tests show the better performance of the studied methods oner the conventional one.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1983.10a
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• pp.112-117
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• 1983

In this paper, a functional m-redundant system, which is me-fault tolerant, is defined based on the graph-theory. This system is designed to be t fault-diagnosable by comparing its unit's outcomes without additive test functions, and so, the system down for diagnosis is not needed. the diagnostic model for this system is presented and this effectively uses system's redundancy. It is shown that this model can be converted into Preparata's model. Thus, the diagnostic characteristics of a functional m-redundant system is analyzed by the methods originated by Preparata et al..