• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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• pp.2625-2628
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• 2003

Phase locked loops are widely used in many applications such as frequency synthesis, clock/data recovery and clock generation. In nearly all the PLL applications, low jitter and fast locking time is required. Without using adaptive loop filter, this paper proposes very simple method for improving locking time and jitter reduction simultaneously in charge pump PLL(CPPLL) using Daul Phase/Frequency Detector(Dual PFD). Based on the proposed scheme, the lock time is improved by 23.1％, and the jitter is reduced by 45.2％ compared with typical CPPLL.

• 한국안전학회지
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• 제22권5호
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• pp.21-26
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• 2007

The computer program is developed to simulate the evacauation time for a building which is made geometrically complex. The program is intended for use both as a search and a design tool to analyze the evacuation safety through a wide range of structure environments. The computer program has a function of importing FDS's result to each individual resident in the building. These attributes include a walking speed reduction by producing visibility reduction for each person on the fire. $A^*$ pathfinding algorithm is adopted to calculate the simulation of escape movement, overtaking, route deviation, and adjustments to individual speeds due to the proximity of crowd members. Finally, a case study for a theater is presented to compared the calculated evacuation time with SIMULEX in detail. This program contribute to a computer program that evaluates the evacuation time of individual occupants as they walk towards, and through the exits especially for building, underground spaces like a subway or tunnel.

• 전기학회논문지
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• 제58권3호
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• pp.516-522
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• 2009

The dimmable magnetic ballast which applies the variable inductor needs a switching process for the dimming process, and it consists of mechanical relays because of costs and reliabilities. However, it is hard to operate with correct timing in mechanical relay, so relays reduce their own life time in inductive applications. Moreover this creates a destructive problem at the switching process. The life time reduction of relays means the life time reduction of the ballast. Thus, in this paper, we described the problem at the witching process in the dimmable magnetic ballast with a variable inductor, which consists of relays and the soft AC switching method in order to solve the problems. As result, we achieved the improvement of the life time and reliability of the ballast.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 추계학술대회 논문집 전력기술부문
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• pp.9-11
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• 2006

This paper suggests a revision method for historical fault data using Proportional Aging Reduction(PAR) to consider maintenance effect in time-varying failure rate. In order to product time-varying failure rate, the historical fault data are necessary. However, the maintenance record could be left out in historical data by spot operator's mistake. In this case, the failure rate is produced less than the average failure rate for increasing equipments' life-time by maintenance effect. Hence, it is necessary for new time-varying failure rate to extract maintenance effect from the existing fault data. In this paper, the revision method to reduce equipments' life-time, adversely using PAR among three techniques to consider maintenance effect.

• Journal of information and communication convergence engineering
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• 제7권4호
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• pp.496-500
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• 2009

In EBCOT, the context modeling process takes excessive calculation time and this paper proposed a method to reduce this calculation time. That is, if the finest resolution coefficient is less than a pre-defined transfer factor the coefficient and its descendents skip the context modeling process. There is a trade-off relationship between the calculation time and the image quality or the amount of output data such that as this threshold value increases, the calculation time and the amount of output data decreases, but the image degradation increases. The experimental results showed that in this range the resulting reduction rate in calculation time was from 3% to 64% in average, the reduction rate in output data was from 32% to 73% in average.

• Smart Structures and Systems
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• 제8권5호
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• pp.449-470
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• 2011

During the last thirty years many structural control concepts have been proposed for the reduction of the structural response caused by earthquake excitations. Their research and implementation in practice have shown that seismic control of structures has a lot of potential but also many limitations. In this paper the importance of two practical issues, time delay and saturation effect, on the performance of controlled structures, is discussed. Their influence, both separately and in interaction, on the response of structures controlled by a modified pole placement algorithm is investigated. Characteristic buildings controlled by this algorithm and subjected to dynamic loads, such as harmonic signals and actual seismic events, are analyzed for a range of levels of time delay and saturation capacity of the control devices. The response reduction surfaces for the combined influence of time delay and force saturation of the controlled buildings are obtained. Conclusions regarding the choice of the control system and the desired properties of the control devices are drawn.

• 제어로봇시스템학회논문지
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• 제13권9호
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• pp.915-919
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• 2007

This paper proposed a transponder detection method to reduce recognition time in RFID system. It's also shown that conventional procedure of communication in the system could cause a waste of time when a reader recognizes a transponder. The reduction of recognition time can be obtained by developing a circuit to detect a transponder actively. Detecting a transponder is achieved by using the voltage variation of reader antenna voltage that happens when a transponder approaches to the vicinity of magnetic field formed by the reader. By adding a comparator to the antenna receiver of a reader, the reader can perceive approach or existence of a transponder. A reader for experiment is made using the MFRC500 by Phillips that supports ISO/IEC 14443 protocol. Comparing the proposed method with the conventional methods by experiment, there are 47.5ms reduction of recognition time maximally and 12ms in average.

• 소성∙가공
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• 제14권3호
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• pp.269-276
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• 2005

The purpose of this research is the warpage reduction for intake-manifold which is made to the injection molding. Intake-manifold is assembling to ultra sonic welding after forming. Therefore deformation is influence on the performance and manufacture to intake-manifold product. Location and number of gates, filling time, mold temperature, packing time, packing pressure and cooling time are factors that affect the deformation of injection molding product. Therefore, the injection molding characteristics of intake-manifold and the estimated deformation are detected by CAE analysis and compare measuring data in this study.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅳ
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• pp.2451-2454
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• 2003

In this paper, we propose the computation reduction methods of LSP(Line spectrum pairs) transformation that is mainly used in CELP vocoders. In order to decrease the computational time in real root method the characteristic of four proposed algorithms is as the following. First, scheme to reduce the LSP transformation time uses met scale. Developed the second scheme is the control of searching order by the distribution characteristic of LSP parameters. Third, scheme to reduce the LSP transformation time uses voice characteristics. Developed the fourth scheme is the control of searching interval and order by the distribution characteristic of LSP parameters. As a result of searching time, computational amount, transformed LSP parameters, SNR, MOS test, waveform of synthesized speech, speech, spectrogram analysis, searching time reduced about 37.5％, 46.21％, 46.3％, 51.29％ in average, computational amount is reduced about 44.76％, 49.44％, 47.03％, 57.40％. But the transformed LSP parameters of the proposed methods were the same as those of real root method.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.196-198
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• 2007

A circuit design technique to reduce the propagation time is proposed for the analog parallel processing-based Viterbi decoder. The analog Viterbi decoder implements the function of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The decoder is for the PR(1.2,2.1) signal of DVD. The benefits are low power consumption and less silicon occupation. In this paper, a propagation time reduction technique is proposed by minimizing the parasitic capacitance components in the layout design of the analog Viterbi decoder. The propagation time reduction effect of the proposed technique has been shown via HSPICE simulation.