• Journal of Korean Society on Water Environment
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• v.24 no.3
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• pp.297-305
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• 2008

It is necessary to select proper reduction methods and to calculate reasonably reduction amount for making good practice of the reduction scheme. Moreover, it is suggested that the reduction amount have to be distributed properly during the planning period. In other words, it has not to be concentrated on the specific year (especially final year of the planning period). The reason why, if the reduction amount concentrate on the final year of the planning period, allotment loading amount could not be achieved in some cases (e.g., insufficiency of budget, extension of construction duration). Even though much of the budget have been supported from national treasury (about 50%), it is thought the role of the local government must be strengthened gradually.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.2
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• pp.243-252
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• 2023

As an efficient key recovery attack on SIDH/SIKE was proposed, CSIDH is drawing attention again. CSIDH is an isogeny-based key exchange algorithm that is safe against known attacks to date, and provide efficient NIKE by modernizing CRS scheme. In this paper, we firstly present the optimized implementation of CSIDH-512 on ARM Cortex-M7. We use three-level hybrid Montgomery reduction and present the results of our implementation, limitations, and future research directions. This is a CSIDH implementation in 32-bit embedded devices that has not been previously presented, and it is expected that the results of this paper will be available to implement CSIDH and derived cryptographic algorithms in various embedded environments in the future.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.57-62
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• 2005

In spite of many advantages of OFDM, a major drawback for implementation is a non-linear distortion in the HPA due to a high PAPR problem. In this paper, the Complementary Clipping Transform technique (CCT) for the PAPR reduction of OFDM system is analyzed for the QPSK and QAM mapping data. BER performance and PSD in front of HPA and after HPA are analytically demonstrated.

• Journal of electromagnetic engineering and science
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• v.8 no.3
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• pp.119-128
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• 2008

In this paper, we propose a developing approach of 600 W super high frequency(SHF) traveling wave tube amplifier (TWTA) for communications. Also, we make a TWTA called the experimental-TWTA(ETWTA), which uses a cathode ripple reduction technique to improve RF performance. After implementation, we discuss, and compare it with some other TWTAs. Its RF performance is better than that of other TWTAs. Therefore, this methodology can be used to develop the high power SHF TWTA for communications.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.17 no.32
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• pp.121-126
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• 1994

Setup Time Reduction is an important aspect of the Just-in-Time(JIT) and Zero Inventory(Zl) Concepts since it supports reductions in manufacturing lead times and inventories. It also enables small lot sizes and kanban systems implementation for material flow - achieving major improvements in production floor management. One concept fundamental to the pursuit of JIT production in Japan and other countries is adoption of a setup time reduction. This paper looks at the necessities of setup time reduction and the relations to machine utilization. By using an EOQ model for evaluate the effect of setup time reduction, we get the results that over 75 % reduction in setup time is obtain the desired results in the lot size reduction.

• Communications for Statistical Applications and Methods
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• v.31 no.2
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• pp.179-189
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• 2024

In multivariate regression with a high-dimensional response Y ∈ ℝ^r and a relatively low-dimensional predictor X ∈ ℝ^p (where r ≥ 2), the statistical analysis of such data presents significant challenges due to the exponential increase in the number of parameters as the dimension of the response grows. Most existing dimension reduction techniques primarily focus on reducing the dimension of the predictors (X), not the dimension of the response variable (Y). Yoo and Cook (2008) introduced a response dimension reduction method that preserves information about the conditional mean E(Y | X). Building upon this foundational work, Yoo (2018) proposed two semi-parametric methods, principal response reduction (PRR) and principal fitted response reduction (PFRR), then expanded these methods to unstructured principal fitted response reduction (UPFRR) (Yoo, 2019). This paper reviews these four response dimension reduction methodologies mentioned above. In addition, it introduces the implementation of the mbrdr package in R. The mbrdr is a unique tool in the R community, as it is specifically designed for response dimension reduction, setting it apart from existing dimension reduction packages that focus solely on predictors.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.62 no.4
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• pp.192-197
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• 2013

Road traffic noise barriers being used to reduce the noise, but the city surroundings inhibition, ecosystem disturbance, and it is difficult to maintain. Can enhance or complement the existing noise barrier performance, so that it is necessary to develop an electronic noise-reduction system In this paper, we proposed an electronic road noise reduction devices to reduce road noise for a DSP-based signal processing and analog signal input-output controller. In order to verify the control performance, we performed noise reduction experimentation of ANC by filtered-X LMS algorithm and traffic noise signal injection. The controller is equipped with noise reduction algorithms were tested on the characteristics of directional and omnidirectional speaker.

• Journal of Information Processing Systems
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• v.15 no.4
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• pp.890-903
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• 2019

The single carrier frequency domain equalization (SC-FDE) technology is an important part of the broadband wireless access communication system, which can effectively combat the frequency selective fading in the wireless channel. In SC-FDE communication system, the accuracy of timing synchronization directly affects the performance of the SC-FDE system. In this paper, on the basis of Schmidl timing synchronization algorithm a timing synchronization algorithm suitable for FPGA (field programmable gate array) implementation is proposed. In the FPGA implementation of the timing synchronization algorithm, the sliding window accumulation, quantization processing and amplitude reduction techniques are adopted to reduce the complexity in the implementation of FPGA. The simulation results show that the algorithm can effectively realize the timing synchronization function under the condition of reducing computational complexity and hardware overhead.

• Journal of IKEEE
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• v.24 no.4
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• pp.1028-1033
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• 2020

The existing in-band interference reduction method recommends the physical separation distance between wireless devices and interference signals, and the interference can be suppressed through the separation distance. If the in-band interference signals can be reduced in a wireless device, a margin can be given to the physical separation distance. Since there is an effect of extending the receiver dynamic range of receivers, it is highly useful for interference reduction and improvement method. In this paper, the structure of an in-band analog IRM(Interference Reduction Module) is proposed and the design and implementation of the proposed analog IRM are described. To design an analog IRM, the interference reduction performance according to the delay mismatch, phase error and the number of delay lines that affect the performance of the analog IRM was simulated. The proposed analog IRM composed of 16 delay lines was implemented and the implemented IRM has the interference reduction performance of about 10dB for a 5G(NR-FR1-TM-1.1) signal having a 40MHz bandwidth at a center frequency of 3.32GHz. The analog IRM proposed in this paper can be used as an in-band interference canceller.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.692-704
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• 2005

With the improvement of computer hardware, GPUs(Graphics Processor Units) have tremendous memory bandwidth and computation power. This leads GPUs to use in general purpose computation. Especially, GPU implementation of compute-intensive physics based simulations is actively studied. In the solution of differential equations which are base of physics simulations, tridiagonal matrix systems occur repeatedly by finite-difference approximation. From the point of view of physics based simulations, fast solution of tridiagonal matrix system is important research field. We propose a fast GPU implementation for the solution of tridiagonal matrix systems. In this paper, we implement the cyclic reduction(also known as odd-even reduction) algorithm which is a popular choice for vector processors. We obtained a considerable performance improvement for solving tridiagonal matrix systems over Thomas method and conjugate gradient method. Thomas method is well known as a method for solving tridiagonal matrix systems on CPU and conjugate gradient method has shown good results on GPU. We experimented our proposed method by applying it to heat conduction, advection-diffusion, and shallow water simulations. The results of these simulations have shown a remarkable performance of over 35 frame-per-second on the 1024x1024 grid.