• Journal of the Korean Vacuum Society
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• v.18 no.2
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• pp.147-150
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• 2009

We present a technique for fabricating low leakage organic field-effect transistors by a functional polydimethylsiloxane (PDMS) layer. The technique relies on the photo-chemical process of conversion of the PDMS to a silicon oxide which provides the selective growth of pentacene thin films. The reduced gate leakage current showed ${\sim}10^{-10}$ A in a linear ($V_d=-5\;V$) and saturation ($V_d=-30\;V$) region at $V_g-V_t>0$.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.1
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• pp.24-29
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• 2000

We propose a simple method to control the crystallization depth of amorphous silicon (a-Si) deposited by PECVD or LPCVD during the excimer laser annealing (ELA). Employing the new method, we have formed poly-Si/a-Si double film and fabricated a new poly-Si TFT with vertical a-Si offsets between the poly-Si channel and the source/drain of TFT without any additional photo-lithography process. The maximum leakage current of the new poly-Si TFT decreased about 80% due to the highly resistive vertical a-Si offsets which reduce the peak electric field in drain depletion region and suppress electron-hole pair generation. In ON state, current flows spreading down through broad a-Si cross-section in the vertical a-Si offsets and the current density in the drain depletion region where large electric field is applied is reduced. The stability of poly-Si TFT has been improved noticeably by suppressing trap state generation in drain region which is caused by high current density and large electric field. For example, ON current of the new TFT decreased only 7% at a stress condition where ON current of conventional TFT decreased 89%.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.7
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• pp.72-78
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• 1998

This paper is focused on the fabrication of reliable novel antifuse, which could operate at low voltage along with the improvement in OFF and ON-state properties. The fabricated antifuse consists of Al/BaTi$_{2}$O$_{3}$/SiO$_{2}$/TiW-silicide structure. Through the systematic analyses for bottom metal and the intermetallic insulator, material and electri cproperties were investiaged. TiW-silicide as the bottom electrode had smooth surface with average roughness of 11.angs. at 10X10.mu.m$^{2}$ and was bing kept as-deposited SiO$_{2}$ film stable. Amorphous BaTi$_{2}$O$_{3}$ film as the another insulator was chosen because of its low breakdown strength (2.5MV/cm). breakdown voltage of antifuse is remarkably reduced by using BaTi$_{2}$O$_{3}$ film, and leakage current of that maintained low level due to the SiO$_{2}$ film. Low ON-resistance (46.ohm./.mu.m$^{2}$) and low programming voltage(9.1V) can be obtained in theses antifuses with 220.angs. double insulator layer and 19.6X10$^{-6}$ cm$^{2}$ area, while keeping sufficient OFF-state reliability (less than 1nA).

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.217-222
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• 2003

A new two-dimensional analytical model for the potential distribution and drain-induced barrier lowering (DIBL) effect of fully depleted short-channel Silicon-on-insulator (SOI)-MESFET's has been presented in this paper. The two dimensional potential distribution functions in the active layer of the device is approximated as a simple parabolic function and the two-dimensional Poisson's equation has been solved with suitable boundary conditions to obtain the bottom potential at the Si/oxide layer interface. It is observed that for the SOI-MESFET's, as the gate-length is decreased below a certain limit, the bottom potential is increased and thus the channel barrier between the drain and source is reduced. The similar effect may also be observed by increasing the drain-source voltage if the device is operated in the near threshold or sub-threshold region. This is an electrostatic effect known as the drain-induced barrier lowering (DIBL) in the short-gate SOI-MESFET's. The model has been verified by comparing the results with that of the simulated one obtained by solving the 2-D Poisson's equation numerically by using the pde toolbox of the widely used software MATLAB.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.6
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• pp.580-585
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• 2004

Silicon dioxide (SiO$_2$) is widely used as a gate dielectric material for thin film transistors (TFT) and semiconductor devices. In this paper, SiO$_2$ films were grown by APCVD(Atmospheric Pressure chemical vapor deposition) at the high temperature. Experimental investigations were carried out as a function of $O_2$ gas flow ratios from 0 to 200 1pm. This article presents the SiO$_2$ gate dielectric studies in terms of deposition rate, refrative index, FT-IR, C-V for the gate dielectric layer of thin film transistor applications. We also study defect passivation technique for improvement interface or surface properties in thin films. Our passivation technique is Forming Gas Annealing treatment. FGA acts passivation of interface and surface impurity or defects in SiO$_2$ film. We used RTP system for FGA and gained results that reduced surface fixed charge and trap density of midgap value.

• Korean Journal of Materials Research
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• v.1 no.3
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• pp.125-131
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• 1991

Boron penetration phenomenon of $p^{+}$ silicon gate with as-deposited amorphous or polycrystalline Si upon high temperature annealing was investigated using high frequency C-V (Capacitance-Volt-age) analysis, CCST(Constant Current Stress Test), TEM(Transmission Electron Microscopy) and SIMS(Secondary Ion Mass Spectroscopy), C-V analysis showed that an as-deposited amorphous Si gate resulted in smaller positive shifts in flatband voltage compared wish a polycrystalline Si gate, thus giving 60-80 percent higher charge-to-breakdown of gate oxides. The reduced boron penetration of amorphous Si gate may be attributed to the fewer grain boundaries available for boron diffusion into the gate oxide and the shallower projected range of $BF_2$ implantation. The relation between electron trapping rate and flatband voltage shift was also discussed.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.12
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• pp.2218-2224
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• 2010

Dye-sensitized solar cell (DSC) is a promising alternative solar cell to the conventional silicon solar cell due to several advantages. Development of large scale module is necessary to commercialize the DSC in the near future. A scribing technology of the transparent conductive oxide (TCO) is one of the important technologies on the fabrication of DSC module. A quality of the scribed line on the TCO has a decisive effect on the efficiency of DSC module. Among several scribing technologies, the fiber laser is a suitable for scribing the TCO more precisely and accurately because of their own characteristics. In this study, we try to improve the quality of the TCO scribed line by using the fiber laser. Consequently, the operating parameter of fiber laser is optimized to get the TCO scribed line with good quality. And the fiber laser scribing technology of the TCO is applied to the fabrication of the DSC with optimal operating parameter, operating current 3900mA. As a result, the current density and fill factor are improved and the total efficiency is increased because the internal resistances of DSC such as TCO sheet resistance and the resistance concerned to the electron movement in the $TiO_2$ are reduced. This is analyzed by the electrochemistry impedance spectroscopy (EIS) and the equivalent circuit model of the DSC.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.30 no.5 s.248
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• pp.405-412
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• 2006

In order to realize a stably propagating flame in a narrow channel, flame instabilities resulting from flame-wall interaction should be avoided. In particular flame quenching is a significant issue in micro combustion devices; quenching is caused either by excessive heat loss or by active radical adsorptions at the wall. In this paper, the relative significance of thermal and chemical effects on flame quenching is examined by means of quenching distance measurement. Emphasis is placed on the effects of surface defect density on flame quenching. To investigate chemical quenching phenomenon, thermally grown silicon oxide plates with well-defined defect distribution were prepared. ion implantation technique was used to control defect density, i.e. the number of oxygen vacancies. It has been found that when the surface temperature is under $300^{\circ}C$, the quenching distance is decreased on account of reduced heat loss; as the surface temperature is increased over $300^{\circ}C$, however, quenching distance is increased despite reduced heat loss effect. Such abberant behavior is caused by heterogeneous surface reactions between active radicals and surface defects. The higher defect density, the larger quenching distance. This result means that chemical quenching is governed by radical adsorption that can be parameterized by oxygen vacancy density on the surface.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.434-435
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• 2012

Plasma enhanced chemical vapor deposition (PECVD) silicon dioxide thin films have many applications in semiconductor manufacturing such as inter-level dielectric and gate dielectric metal oxide semiconductor field effect transistors (MOSFETs). Fundamental chemical reaction for the formation of SiO2 includes SiH4 and O2, but mixture of SiH4 and N2O is preferable because of lower hydrogen concentration in the deposited film [1]. It is also known that binding energy of N-N is higher than that of N-O, so the particle generation by molecular reaction can be reduced by reducing reactive nitrogen during the deposition process. However, nitrous oxide (N2O) gives rise to nitric oxide (NO) on reaction with oxygen atoms, which in turn reacts with ozone. NO became a greenhouse gas which is naturally occurred regulating of stratospheric ozone. In fact, it takes global warming effect about 300 times higher than carbon dioxide (CO2). Industries regard that N2O is inevitable for their device fabrication; however, it is worthwhile to develop a marginable nitrous oxide free process for university lab classes considering educational and environmental purpose. In this paper, we developed environmental friendly and material cost efficient SiO2 deposition process by substituting N2O with O2 targeting university hands-on laboratory course. Experiment was performed by two level statistical design of experiment (DOE) with three process parameters including RF power, susceptor temperature, and oxygen gas flow. Responses of interests to optimize the process were deposition rate, film uniformity, surface roughness, and electrical dielectric property. We observed some power like particle formation on wafer in some experiment, and we postulate that the thermal and electrical energy to dissociate gas molecule was relatively lower than other runs. However, we were able to find a marginable process region with less than 3% uniformity requirement in our process optimization goal. Surface roughness measured by atomic force microscopy (AFM) presented some evidence of the agglomeration of silane related particles, and the result was still satisfactory for the purpose of this research. This newly developed SiO2 deposition process is currently under verification with repeated experimental run on 4 inches wafer, and it will be adopted to Semiconductor Material and Process course offered in the Department of Electronic Engineering at Myongji University from spring semester in 2012.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.39-45
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• 2012

Three-dimensional integrated circuit(3D IC) technology has become increasingly important due to the demand for high system performance and functionality. In this work, BOE and HF wet etching of Cu line surfaces after CMP were conducted for Cu-Cu pattern direct bonding. Step height of Cu and $SiO_2$ as well as Cu dishing after Cu CMP were analyzed by the 3D-Profiler. Step height increased and Cu dishing decreased with increasing BOE and HF wet etching times. XPS analysis of Cu surface revealed that Cu surface oxide layer was partially removed by BOE and HF wet etching treatment. BOE treatment showed not only the effective $SiO_2$ etching but also reduced dishing and Cu surface oxide rather than HF treatment, which can be used as an meaningful process data for reliable Cu-Cu pattern bonding characteristics.