• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.267-270
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• 1999

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer (DDFS) is proposed. In the case that ROM is used for sinusoidal value calculation, reducing the size of ROM is significant. So the power consumption is affected mostly by its bit width. In the proposed method, the ROM bit width is reduced by 1 bit using the phase subtraction and the approximation. The spurious level is better than 80㏈c and the power consumption estimated is 510㎼/MHz.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2015년도 전력전자학술대회 논문집
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• pp.159-160
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• 2015

Recently, it is increased to use the portable device with small size. It is also increasing for demand of a small size adapter. To reduce the size of components, switching frequency has to be increased. But it causes higher switching loss and temperature of components. Especially, the temperature of adapter must be limited because adapter can be easily touched when portable device is being charged. To reduce temperature of adapter, high efficiency is essential. To solve this problem, this paper proposes design of resonance frequency optimization for LLC converter with high efficiency and low temperature of passive components.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2005년도 춘계종합학술대회
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• pp.1053-1056
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• 2005

본 논문에서는 ROM 사이즈를 줄이기 위한 디지털 합성기의 설계기법과 그 구현에 관하여 기술한다. 지금까지 제안된 설계기법과는 달리, 본 논문에서 제안하는 기법은 최소한의 부가적 하드웨어만을 사용하여 ROM 사이즈를 대폭 줄일 수 있다. 구현된 디지털 합성기는 입력한 주파수 제어값에 따라 원하는 발진 주파수를 정확하게 합성해내고 있음을 측정결과로부터 확인할 수 있었다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2009년도 추계학술대회
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• pp.401-404
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• 2009

본 논문에서는 ROM의 크기를 줄여 전력 소모를 줄일 수 있는 DDFS를 제안하였다. 새롭게 제안된 병렬 ROM 방식은 두 개의 ROM을 사용하여 원하는 주파수를 합성함으로써 전체적인 ROM들의 크기를 줄여준다. 표본화된 사인파의 양자화 값은 양자화 ROM과 차동 ROM에 저장된다. ROM 크기를 줄이기 위해 사인파를 양자화 할 때 일련의 차동 양자화 기술을 응용, 변형하여 두 개의 병렬 ROM을 사용한 압축방식을 제안한다. 이를 사용함으로써 최대 67.5%의 ROM 크기를 감소시켜 전력소모를 줄일 수 있다.

• International Journal of Computer Science & Network Security
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• 제22권9호
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• pp.327-333
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• 2022

Wireless Sensor Networks (WSNs) plays an important role in our everyday life. WSN is distributed in all the places. Nowadays WSN devices are developing our world as smart and easy to access and user-friendly. The sensor is connected to all the resources based on the uses of devices and the environment [1]. In WSN, Quality of Service is based on time synchronization and scheduling. Scheduling is important in WSN. The schedule is based on time synchronization. Min-Max data size scheduling is used in this proposed work. It is used to reduce the Delay & Energy. In this proposed work, Two-hop neighboring node is used to reduce energy consumption. Data Scheduling is used to identify the shortest path and transmit the data based on weightage. The data size is identified by three size of measurement Min, Max and Medium. The data transmission is based on time, energy, delivery, etc., the data are sent through the first level shortest path, then the data size medium, the second level shortest path is used to send the data, then the data size is small, it should be sent through the third level shortest path.

• 한국정밀공학회지
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• 제21권1호
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• pp.133-139
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• 2004

High speed machining (HSM) can reduce machining time with the high metal removal rate by high speed spindle and feedrate. This paper supports HSM technology using the small size tool with the optimal tool path generation and modification of tool change. The optimum tool path is generated to reduce cutting length of cavity pattern and change the cutting tool for preventing the tool breakage by wear. The tool path is modified with the experiment data of tool wear and breakage to support tool change on reasonable time. The result can contribute to HSM technology of high hardness materials using the small size end-mill.

• ETRI Journal
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• 제25권5호
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• pp.297-304
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• 2003

A multimedia SoC often requires a large internal buffer, because it must store the whole search window to reduce the huge I/O bandwidth of motion estimation. However, the silicon area of the internal buffer increases tremendously as the search range becomes larger. This paper proposes a new method that greatly reduces the internal buffer size of a multimedia SoC while the computational cost, I/O bandwidth, and image quality do not change. In the proposed method, only the overlapped parts of search windows for consecutive macroblocks are stored in the internal buffer. The proposed method reduces the internal buffer. The proposed method reduces the internal buffer size to 1/5.0 and 1/8.8 when the search range is ${\pm}64{\times}{\pm}$64 and ${\pm}128{\times}{\pm}$128, respectively.

• 한국컴퓨터정보학회논문지
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• 제21권4호
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• pp.1-8
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• 2016

In small embedded systems including IoT devices, memory size is very small and it is important to reduce memory amount for execution of application programs. For multi-threaded applications, stack may consume a large amount of memory because each thread has its own stack of sufficiently large size for worst case. This paper presents an implementation of single stack multi-threading, called SSThread (Single Stack Thread), by sharing a stack for all threads to reduce stack memory size. By using SSThread, multi-threaded applications can be programmed based on normal C language environment and there is no requirement of transporting multi-threading operating systems. It consists of several library functions and various C macro definitions. Even though some functional restrictions in comparison to operating systems supporting complete multi-thread functionalities, it is very useful for small embedded systems with tiny memory size and it is simple to setup programming environment for multi-thread applications.

• 설비공학논문집
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• 제18권7호
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• pp.556-562
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• 2006

The objectives of this paper are to analyze simultaneous heat and mass transfer performance for a plate type bubble absorber with binary nanofluids numerically and to investigate the effects of binary nanofluids and surfactants on the size of the bubble absorber. The effective absorption ratio represents the effect of binary nanofluids and surfactants on the absorption performance. The kinds and concentrations of nano-particles and surfactants are considered as the key parameters. The results show that the addition of surfactants can reduce the size of absorber up to 74.4%, the application of binary nanofluids does the size up to 63.6%. Combination of binary nanofluids and surfactants can reduce the size of absorber up to 77.4%.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.782-785
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• 2002

Power amplifier of wireless communication tranceiver can be effectually controlled output power. And small size and low power dissipation are indispensable to portable system. In this paper, to reduce the size of portable tranceiver, inductor is integrated in a single chip. And to reduce power dissipation, a power amplifier that can be digitally controlled output power, is proposed and designed.