• Title/Summary/Keyword: Reduce Integration

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Framework for Information Integration and Customization Using Ontology and Case-based Reasoning (온톨로지 및 사례기반추론을 이용한 맞춤형 통합 정보 생성 프레임워크의 제안)

  • Lee, Hyun-Jung;Sohn, M-Ye
    • Journal of Intelligence and Information Systems
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    • v.15 no.4
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    • pp.141-158
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    • 2009
  • The requirements of knowledge customization have increased as information resources have become more various and the numbers of the resources are increased. Even if the method for collecting the information has improved like Really Simple Syndication (RSS), information users are still struggling for extracting and customizing the required information through the Web. To reduce the burden, we offer the dynamic knowledge customization framework by using ontology-based CBR. The framework consisting of three phases is comprised of the conversion phase of web information as a machine-accessible case, the extraction phase to find a case appropriate for information users' requirements, and the case customization phase to create knowledge depending on information user's requirements. Newly, the dynamic and intensity-based similarity is adopted to support timely dynamic change of users' requirements. The framework has adopted to create traveler's knowledge to the level users wanted.

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Object Localization in Sensor Network using the Infrared Light based Sector and Inertial Measurement Unit Information (적외선기반 구역정보와 관성항법장치정보를 이용한 센서 네트워크 환경에서의 물체위치 추정)

  • Lee, Min-Young;Lee, Soo-Yong
    • Journal of Institute of Control, Robotics and Systems
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    • v.16 no.12
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    • pp.1167-1175
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    • 2010
  • This paper presents the use of the inertial measurement unit information and the infrared sector information for getting the position of an object. Travel distance is usually calculated from the double integration of the accelerometer output with respect to time; however, the accumulated errors due to the drift are inevitable. The orientation change of the accelerometer also causes error because the gravity is added to the measured acceleration. Unless three axis orientations are completely identified, the accelerometer alone does not provide correct acceleration for estimating the travel distance. We propose a way of minimizing the error due to the change of the orientation. In order to reduce the accumulated error, the infrared sector information is fused with the inertial measurement unit information. Infrared sector information has highly deterministic characteristics, different from RFID. By putting several infrared emitters on the ceiling, the floor is divided into many different sectors and each sector is set to have a unique identification. Infrared light based sector information tells the sector the object is in, but the size of the uncertainty is too large if only the sector information is used. This paper presents an algorithm which combines both the inertial measurement unit information and the sector information so that the size of the uncertainty becomes smaller. It also introduces a framework which can be used with other types of the artificial landmarks. The characteristics of the developed infrared light based sector and the proposed algorithm are verified from the experiments.

Strategies for Successful Supplier Relationship Management(SRM) in the SI Industry (SI 산업의 공급자관계관리(SRM) 모델 : 전략적 파트너십 협력관계로의 발전)

  • Cha, Kyung-Jin;Lee, Zoon-Ky;Cha, Joon-Seub
    • The Journal of Society for e-Business Studies
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    • v.17 no.3
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    • pp.105-116
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    • 2012
  • In the system integration (SI) industry, improving relationships with outsourcing partners is one of the key challenges faced by SI companies that aim to increase productivity and reduce costs. In the SI industry, over 80% of project development work is performed by these outsourcing partners. Hence, large SI companies focus on fostering high-performing partners through improved cooperation and mutual relations. However, in the SI industry the existing process of managing outsourcing partners is unable to advance to the level of long-term partnerships due to inadequate information sharing and communication in the process of selecting and assessing a potential and existing partner. Based on the theory of partnership, this study identifies the success factors for new strategic partnerships. Further, this study presents a model for assessing partner companies to promote increased productivity and improve the relationship between an SI company and its partner. In addition, this model is used to assess partner relationships for a well-known SI company "A". This study explores the feasibility of a new framework model.

Time Series Analysis on the Endogeneity between Quality of Internet Banking System and Business Performances of Banks (인터넷뱅킹시스템의 품질과 은행의 영업성과 간 내생성에 대한 시계열 분석)

  • Shim, Seonyoung
    • The Journal of Society for e-Business Studies
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    • v.18 no.4
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    • pp.169-193
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    • 2013
  • This study investigates time series data on internet banking systems and business performances for 5 large-scale banks : Kookmin, Woori, Hana, City, Shinhan. These banks have the common features that they merged with other banks around 2000, hence they experienced massive IS integration between banks. This study adopted VAR and VECM for identifying Granger causality between the quality of internet banking systems and the performances of banks(operating revenue and cost). The main results are as follows. First, internet banking system impacts positively on the revenues as well as costs of banks. Second, the improvement of internet banking system is instigated by cost part more than revenue part. Hence, the results imply that banks tries to reduce operating costs via internet banking systems, however the systems rather increased the costs of banks, although the systems increased operating revenues of banks too.

A Low-Complexity Real-Time Barrel Distortion Correction Processor Combined with Color Demosaicking (컬러 디모자이킹이 결합된 저 복잡도의 실시간 배럴 왜곡 보정 프로세서)

  • Jeong, Hui-Seong;Park, Yun-Ju;Kim, Tae-Hwan
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.9
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    • pp.57-66
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    • 2014
  • This paper presents a low-complexity barrel distortion correction processor for wide-angle cameras. The proposed processor performs the barrel distortion correction jointly with the color demosaicking, so that the hardware complexity can be reduced significantly. In addition, to reduce the required memory bandwidth, an efficient memory interface is proposed by utilizing the spatial locality of the memory access in the correction process. The proposed processor is implemented with 35K logic gates in a $0.11-{\mu}m$ CMOS process and its correction speed is 150 Mpixels/s at the operating frequency of 606MHz, where the supported frame size is $2048{\times}2048$ and the required memory bandwidth is 1 read/cycle.

Application of Partnering to Design VE to Public Design-Build Projects (공공부문 일괄입찰사업의 설계VE 파트너링 활용방안)

  • Kim, Hae-Gon;Um, Ik-Jun;Koo, Kyo-Jin;Hyun, Chang-Taek
    • Korean Journal of Construction Engineering and Management
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    • v.7 no.1 s.29
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    • pp.110-118
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    • 2006
  • Current design-build contract is the type of joint venture, but performs by separate party which causes change orders due to the lack of communication between design and construction, so it cannot lead the main object which is the integration of design and construction. Furthermore, the current design-build contract is impossible to reduce the project costs by VE at the design development phase because the design proceeds with the fixed price through bidding. Like these limitless, the analysis results of the case of VE in the design-build projects, several problems that are prevented from active design VE are elicited by the project participants. Meanwhile, Ministry of Construction & Transportation decided to enlarge the VE review system lately. Therefore, in this study, it presented model of design VE partnering of design-build and partnering agreements form to apply design VE and to try to be able to lead the design VE to be more successful in public design-build projects.

Performance Analysis of Stepwise Parallel Processing for Cell Search in WCDMA over Rayleigh Fading Channels (레일리 페이딩 채널에서 WCDMA의 단계별 병렬 처리 셀 탐색의 성능 해석)

  • 송문규
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.2B
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    • pp.125-136
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    • 2002
  • It is very important to acquire the synchronization in a intercell asynchronous WCDMA system, and it is carried out through the three-step cell search process. The cell search can operate in a stepwise parallel manner, where each step works in pipelined operation, to reduce the cell search time. In case that the execution time is set to be the same in each step, excessive accumulations will be caused in both step 1 and step 3, because step 2 should take at least one frame for its processing. In general, the effect of post-detection integration becomes saturated as the number of the accumulations increases. Therefore, the stepwise parallel scheme does not give much enhancement. In this paper, the performance of the stepwise parallel processing for cell search in WCDMA system is analyzed over Rayleigh fading channels. Through the analysis, the effect of cell search parameters such as the number of accumulations in each step and the power ratio allocated among channels is investigated. In addition, the performance of the stepwise parallel cell search is improved by adjusting the execution time appropriately for each step and is compared with that of the conventional stepwise serial processing.

Performance Analysis of Packet CDMA R-ALOHA for Multi-media Integration in Cellular Systems with Adaptive Access Permission Probability

  • Kyeong Hur;Eom, Doo-Seop;Tchah, Kyun-Hyon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.12B
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    • pp.2109-2119
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    • 2000
  • In this paper, the Packet CDMA Reservation ALOHA protocol is proposed to support the multi-traffic services such as voice and videophone services with handoff calls, high-rate data and low-rate data services efficiently on the multi-rate transmission in uplink cellular systems. The frame structure, composed of the access slot and the transmission slot, and the proposed access permission probability based on the estimated number of contending users for each service are presented to reduce MAI. The assured priority to the voice and the videophone handoff calls is given through higher access permission probability. And through the proposed code assignment scheme, the voice service can be provided without the voice packet dropping probability in the CDMA/PRMA protocols. The code reservation is allowed to the voice and the videophone services. The low-rate data service uses the available codes during the silent periods of voice calls and the remaining codes in the codes assigned to the voice service to utilize codes efficiently. The high-rate data service uses the assigned codes to the high-rate data service and the remaining codes in the codes assigned to the videophone service. Using the Markov-chain subsystem model for each service including the handoff calls in uplink cellular systems, the steady-state performances are simulated and analyzed. After a round of tests for the examples, through the proposed code assignment scheme and the access permission probability, the Packet CDMA Reservation ALOHA protocol can guarantee the priority and the constant QoS for the handoff calls even at large number of contending users. Also, the data services are integrated efficiently on the multi-rate transmission.

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Macro-model for Estimation of Maximum Power Dissipation of CMOS Digital Gates (CMOS 디지털 게이트의 최대소모전력 예측 매크로 모델)

  • Kim, Dong-Wook
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.48 no.10
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    • pp.1317-1326
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    • 1999
  • As the integration ratio and operation speed increase, it has become an important problem to estimate the dissipated power during the design procedure as a method to reduce the TTM(time to market). This paper proposed a prediction model to estimate the maximum dissipated power of a CMOS logic gate. This model uses a calculational method. It was formed by including the characteristics of MOSFETs of which a CMOS gate consists, the operational characteristics of the gate, and the characteristics of the input signals. As the modeling process, a maximum power estimation model for CMOS inverter was formed first, and then a conversion model to convert a multiple input CMOS gate into a corresponding CMOS inverter was proposed. Finally, the power model for inverter was applied to the converted result so that the model could be applied to a general CMOS gate. For experiment, several CMOS gates were designed in layout level by $0.6{\mu}m$ layout design rule. The result by comparing the calculated results with those from HSPICE simulations for the gates showed that the gate conversion model has within 5% of the relative error rate to the SPICE and the maximum power estimation model has within 10% of the relative error rate. Thus, the proposed models have sufficient accuracies. Also in calculation time, the proposed models was more than 30 times faster than SPICE simulation. Consequently, it can be said that the proposed model could be used efficiently to estimate the maximum dissipated power of a CMOS logic gate during the design procedure.

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Sphere Decoding Algorithm and VLSI Implementation Using Two-Level Search (2 레벨 탐색을 이용한 스피어 디코딩 알고리즘과 VLSI 구현)

  • Huynh, Tronganh;Cho, Jong-Min;Kim, Jin-Sang;Cho, Won-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.6
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    • pp.104-110
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    • 2008
  • In this paper, a novel 2-level-search sphere decoding algorithm for multiple-input multiple-output (MIMO) detection and its VLSI implementation are presented. The proposed algorithm extends the search space by concurrently performing symbol detection on 2 level of the tree search. Therefore, the possibility of discarding good candidates can be avoided. Simulation results demonstrate the good performance of the proposed algorithm in terms of bit-error-rate (BER). From the proposed algorithm, an efficient very large scale integration (VLSI) architecture which incorporates low-complexity and fixed throughput features is proposed. The proposed architecture supports many modulation techniques such as BPSK, QPSK, 16-QAM and 64-QAM. The sorting block, which occupies a large portion of hardware utilization, is shared for different operating modes to reduce the area. The proposed hardware implementation results show the improvement in terms of area and BER performance compared with existing architectures.