• ETRI Journal
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• v.32 no.2
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• pp.222-229
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• 2010

A conventional pseudorandom sequence generator creates only 1 bit of data per clock cycle. Therefore, it may cause a delay in data communications. In this paper, we propose an efficient implementation method for a pseudorandom sequence generator with parallel outputs. By virtue of the simple matrix multiplications, we derive a well-organized recursive formula and realize a pseudorandom sequence generator with multiple outputs. Experimental results show that, although the total area of the proposed scheme is 3% to 13% larger than that of the existing scheme, our parallel architecture improves the throughput by 2, 4, and 6 times compared with the existing scheme based on a single output. In addition, we apply our approach to a $2{\times}2$ multiple input/multiple output (MIMO) detector targeting the 3rd Generation Partnership Project Long Term Evolution (3GPP LTE) system. Therefore, the throughput of the MIMO detector is significantly enhanced by parallel processing of data communications.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.679-682
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• 1998

This paper presents the VLSI implementation of RS(reed-solomon) decoder using the Modified Euclidean Algorithm(hereafter MEA) for DVD(Digital Versatile Disc) and CD(Compact Disc). The decoder has a capability of correcting 8-error or 16-erasure for DVD and 2-error or 4-erasure for CD. The technique of polynomial evaluation is introduced to realize syndrome calculation and a polynomial expansion circuit is developed to calculate the Forney syndrome polynomial and the erasure locator polynomial. Due to the property of our system with buffer memory, the MEA architecture can have a recursive structure which the number of basic operating cells can be reduced to one. We also proposed five criteria to determine an uncorrectable codeword in using the MEA. The overall architecture is a simple and regular and has a 4-stage pipelined structure.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.4
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• pp.156-163
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• 1996

In this paper, we described the implementation and the sound quality assessment of a real-time stereo audio codec using TMS320C40 DSP (digital signal processing) chip for low bitrte and high quality audio. We implemented hardware and software in order to overcome a real-time processing problem of audio compression algorithm that can be produced by largely recursive computing and complexity of the process. We have studied five types of distortion that can be produced by perceptual coding and the codec was evaluated by eight test musics that are selected in SQAM (sound quality assessment material) 422-2-4-2 produced by EBU (european broadcast union). The subjective listening tests were carried out on the codec quality and preformance by double blind method in a listening room with eleven listeners. As a result, 5 grade-impairment scale was scored under minus one and the codec quality was evaluated to be perceptible, but not annoying.

• Journal of the Korea Society of Computer and Information
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• v.4 no.4
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• pp.94-100
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• 1999

This paper concerns the implementation of a digital neural network which performs the high speed operation of Hopfield model's arithmetic operation. It is also designed to use a look-up table and produce floating point arithmetic of nonlinear function with high speed operation. The arithmetic processing of Hopfleld is able to describe the matrix-vector operation, which is adaptable to design the array processor because of its recursive and iterative operation .The proposed method is expected to be applied to the field of real neural networks because of the realization of the current VLSI techniques.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.11
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• pp.17-26
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• 1993

In this paper, a VlSI architecture for Reed-Solomon (RS) decoder based on the Berlekamp algorithm is proposed. The proposed decoder provided both erasure and error correcting capability. In order to reduc the chip area, we reformulate the Berlekamp algorithm. The proposed algorithm possesses a recursive structure so that the number of cells for computing the errata locator polynomial can be reduced. Moreover, in our approach, only one finite field multiplication per clock cycle is required for implementation, provided an improvement in the decoding speed, and the overall architecture features parallel and pipelined structure, making a real time decoding possible. From the performance evaluation, it is concluded that the proposed VLSI architecture is more efficient in terms of VLSI implementation than the rcursive architecture based on the Euclid algorithm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.8
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• pp.1428-1436
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• 2000

An adaptive predistorter linearizer suitable for the DSP implementation is proposed. Predistortion is performed by the DSP instead of the analog predistorter. RLS algorithm is employed for the optimization process to minimize the errors between the predistorter and postdistorter output signals. Computer simulation results for our linearizer show good performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.4
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• pp.961-971
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• 1996

The effect of inband TDMA narrow band jammers to DS-CDMA system performance and the suppression techniques are investigated using Monte Carlo simulations. TIA stantard North American Digital Cellular wea used as jammer. Levinson Dubin and conventional recursive least square algorithm were emphasized since these techniques can be implemented with a few DSPs for CDMA application. Two filter structures, i.e., complex suppression filter and real suppression filter in each inphase and quadrature channels, are investigated and their performances are compared. Complex suppression filter with Levinson Durbin algorithm of 20msec updata rate is the most promising with respect to implementation and performance poit of view. Implementation feasibility is discussed and the channel capacity lost by suppression is computed.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.398-400
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• 1996

We present the implementation of the adaptive filter for EMG signal processing using VHDL. For making ASIC, the basic FPU(floating point processor), e.g., adder, multiplier and divider, are implemented with VHDL. The FPU is simulated and the controller for the RLSL(recursive least square lattice) algorithm of the adaptive filter is implemented. Then FPU and the controller are linked and simulated. Finally the models are synthesized and the gate level is implemented.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.1
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• pp.23-30
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• 1980

The reconstruction problem in a low dose case requires some compromise of resolution and noise artifacts, and also some modification of filter kernels depending on the signal-to-noise ratio of projection data. In this paper, ail algorithm for the reconstruction of an image function from noisy projection data is suggested, based on minimum-mean-square error criterion. Modification of the falter kernel is made from information (statistics) obtained from the projection data. The simulation study Proves that this algorithm, based on the Wiener falter approach, provides substantially improved image with reduction of noise as well as improvement of the resolution. An approximate method was also studied which leads to the possible use of a recursive filter in the convolution process of image reconstruction.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.1
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• pp.75-85
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• 1985

We have studied on the 2-D moving target tracking algorithm satisfying a real-time hardware implementation requirement. In this paper, a fast algorithm is developed based on the operator formulation and the variational algorithm f 10] . Here, we use the directed search for the maximum of the cross-correlation in order to obtain an initial estimate for the variational algorithm and decompose the scene into 16 smaller subblocks and apply the variational algorithm to each subblock sequentially with a new moving area detection method. We call the algorithm subblock based recursive algorithm. Compared with (10) , the ratio of the computational savings obtained from the proposed algorithm is 7 on the average.