• Journal of Applied Reliability
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• v.14 no.2
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• pp.103-107
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• 2014

An algorithm to get network reliability, where each link has probability of fuzzy number, is proposed. Decomposition method and fuzzy numbers arithmetic are applied to the algorithm. Pivot link is chosen one by one from start node recursively at time of decomposition, and arithmetic of fuzzy complementary numbers is included at the same time. No criteria of pivot link selection and the recursive calculation make the algorithm simple.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.12
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• pp.1079-1085
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• 2013

Due to the limited power supply resources, it is essential that the minimization of algorithmic operation and the reduction of the hardware logical-resources in the design of the satellite transponder. It is also required that the transponder process the signals of various bandwidth efficiently, that is suitble for the SDR-based implementation. This paper proposes a variable rate down sampler which can provide variable bandwidth and data rate for carrier, ranging and sub-band command signals respectively. The proposed down sampler can provide multiple $2^M$ decimated outputs from a single half band filter with recursive arithmetic architecture, which can minimize the hardware resources as well as the arithmetic operations. The algorithm for hardware implementation as well as the analysis for the passband flatness and aliasing is presented and varified by the FPGA implementation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.2
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• pp.204-210
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• 1988

The residue number system offers the possibility of high-speed operation and error detection/correction because of the separability of arithmetic operations on each digit. A compact residue arithmetic module named the self-checking pulse-train residue arithmetic circuit is effectively employed as the basic module, and an efficient error detection/correction algorithm in which error detection is performed in each basic module and error correction is performed based on the parallelism of residue arithmetic is also employed. In this case, the error correcting circuit is imposed in series to non-redundant system. This design method has an advantage of compact hardware. Following the proposed method, a 2nd-order recursive fault-tolerant digital filter is practically implemented, and its fault-tolerant ability is proved by noise injection testing.

• Journal of Electrical Engineering and Technology
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• v.7 no.6
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• pp.1014-1022
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• 2012

This paper proposes a modified recursive sliding DFT to measure the phase of a single-tone. The modification is to provide a self error-cancelling mechanism so that it can significantly reduce the numerical error, which is generally introduced and accumulated when a recursive algorithm is implemented in finite wordlength arithmetic. The phase measurement error is analytically derived to suggest optimized distributions of quantization bits. The analytic derivation and the robustness of the algorithm are also verified by computer simulations. It shows that the maximum phase error of less than $5{\times}10^{-2}$ radian is obtained even when the algorithm is coarsely implemented with 4-bit wordlength twiddle factors.

• Journal of the Korea Society of Computer and Information
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• v.4 no.4
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• pp.94-100
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• 1999

This paper concerns the implementation of a digital neural network which performs the high speed operation of Hopfield model's arithmetic operation. It is also designed to use a look-up table and produce floating point arithmetic of nonlinear function with high speed operation. The arithmetic processing of Hopfleld is able to describe the matrix-vector operation, which is adaptable to design the array processor because of its recursive and iterative operation .The proposed method is expected to be applied to the field of real neural networks because of the realization of the current VLSI techniques.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.4
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• pp.7-14
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• 2003

A number of embedded wavelet image coding methods have been proposed since the introduction of EZW(Embedded Zerotree Wavelet) algorithm. A common characteristic of these methods is that they use fundamental ideas found in the EZW algorithm. Especially, one of these methods is the SPIHT(Set Partitioning in Hierarchy Trees) algorithm, which became very popular since it was able to achieve equal or better performance than EZW without having to use an arithmetic encoder. In this paper We propose a recursive set partitioning in hierarchy trees(RSPIHT) algorithm for embedded image coding and evaluate it's effectiveness experimentally. The proposed RSPIHT algorithm takes the simple and regular form and the worst case time complexity of O(n). From the viewpoint of processing time, the RSPIHT algorithm takes about 16.4% improvement in average than the SPIHT algorithm at T-layer over 4 of experimental images. Also from the viewpoint of coding rate, the RSPIHT algorithm takes similar results at T-layer under 7 but the improved results at other T-layer of experimental images.

• Journal of Advanced Navigation Technology
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• v.19 no.6
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• pp.614-622
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• 2015

Binary MQ arithmetic coding is widely used recently as a basic entropy coder in multimedia coding system. MQ coder esteems high in compression efficiency to be used in JBIG2 and JPEG2000. The importance of arithmetic coding is increasing after it is adopted as an unique entropy coder in HEVC standard. In the binary MQ coder, arithmetic approximation without multiplication is used in the process of recursive subdivision of range interval. Because of the MPS/LPS exchange activity happened in MQ coder, output byte tends to increase. This paper proposes an enhanced binary MQ arithmetic coder to make use of a lookup table for AQe using quantization skill in order to reduce the deficiency. Experimental results show that about 4% improvement of compression in case of JBIG2 for bi-level image compression standard. And also, about 1% improvement of compression ratio is obtained in case of lossless JPEG2000 coding. For the lossy JPEG2000 coding, about 1% improvement of PSNR at the same compression ratio. Additionally, computational complexity is not increasing.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• The Transactions of the Korea Information Processing Society
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• v.2 no.5
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• pp.677-690
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• 1995

In this paper, we propose the high efficiency data compression capable of error control using block-sorting, move to front(MTF) and arithmetic code with variable length in to fixed out. First, the substring with is parsed into length N is shifted one by one symbol. The cyclic shifted rows are sorted in lexicographical order. Second, the MTF technique is applied to get the reference of locality in the sorted substring. Then the preprocessed sequence is coded using VF(variable to fixed) arithmetic code which can be limited the error propagation in one codeword. The key point is how to split the fixed length codeword in proportion to symbol probabilities in VF arithmetic code. We develop the new VF arithmetic coding that split completely the codeword set for arbitrary source alphabet. In addition to, an extended representation for symbol probability is designed by using recursive Gray conversion. The performance of proposed method is compared with other well-known source coding methods with respect to entropy, compression ratio and coding times.

• The Journal of the Acoustical Society of Korea
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• v.16 no.3
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• pp.94-98
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• 1997

The most commonly used method to generate sonar transmitting beam is extracting digital samples out of memory, which are to excite transducers of the phased array respectively. As several types of signals have been used in sonar to enhance the performance of sonar in various environments, a large amount of memory is required to store them. In this paper, we adopt recursive algorithm to synthesize every different time-delayed signal for transmitting beams with small amount of memory and simple arithmetic operations. The error due to recursive calculation is also analyzed.