• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.1886-1900
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• 2018

This paper proposes a confronting feedback control structure and controllers for positive output elementary super lift Luo converters (POESLLCs) working in discontinuous conduction mode (DCM). The POESLLC offers the merits like high voltage transfer gain, good efficiency, and minimized coil current and capacitor voltage ripples. The POESLLC working in DCM holds the value of not having right half pole zero (RHPZ) in their control to output transfer function unlike continuous conduction mode (CCM). Also the DCM bestows superlative dynamic response, eliminates the reverse recovery troubles of diode and retains the stability. The proposed control structure involves two controllers respectively to control the voltage (outer) loop and the current (inner) loop to confront the time-varying ON/OFF characteristics of variable structured systems (VSSs) like POESLLC. This study involves two different combination of feedback controllers viz. the proportional integral controller (PIC) plus sliding mode controller (SMC) and the fuzzy logic controller (FLC) plus SMC. The state space averaging modeling of POESLLC in DCM is reviewed first, then design of PIC, FLC and SMC are detailed. The performance of developed controller combinations is studied at different working states of the POESLLC system by MATLAB-Simulink implementation. Further the experimental corroboration is done through implementation of the developed controllers in PIC 16F877A processor. The prototype uses IRF250 MOSFET, IR2110 driver and UF5408 diodes. The results reassured the proficiency of designed FLC plus SMC combination over its counterpart PIC plus SMC.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.32 no.4
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• pp.607-615
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• 2022

The SITM (See-In-The-Middle) proposed in CHES 2020 is a methodology for side-channel assisted differential cryptanalysis. This technique analyzes the power traces of unmasked middle rounds in partial masked SPN block cipher implementation, and performs differential analysis with the side channel information. Blockcipher GIFT is a lightweight blockcipher proposed in CHES 2017, designed to correct the well-known weaknesses of block cipher PRESENT and provide the efficient implementation. In this paper, we propose SITM attacks on partial masked implementation of GIFT-128. This attack targets 4-round and 6-round masked implementation of GIFT-128 and time/data complexity is 2^14.01 /2^14.01, 2¹⁶ /2¹⁶. In this paper, we compare the masterkey recovery logic available in SITM attacks, establishing a criterion for selecting more efficient logic depending on the situation. Finally, We introduce how to apply the this attack to GIFT-COFB, one of the finalist candidates in NIST lightweight cryptography standardization process.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.480-480
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• 2000

In this paper, we proposed a fuzzy-neuro controller to control the speed of wound rotor induction motor with slip energy recovery. The speed is limited at some range of sub-synchronous speed of the rotating magnetic field. Control speed by adjusting resistance value in the rotor circuit that occurs the efficiency of power are reduced, because of the slip energy is lost when it passes through the rotor resistance. The control system is designed to maintain efficiency of motor. Recently, the emergence of artificial neural networks has made it conductive to integrate fuzzy controllers and neural models for the development of fuzzy control systems, Fuzzy-neuro controller has been designed by integrating two neural network models with a basic fuzzy logic controller. Using the back propagation algorithm, the first neural network is trained as a plant emulator and the second neural network is used as a compensator for the basic fuzzy controller to improve its performance on-line. The function of the neural network plant emulator is to provide the correct error signal at the output of the neural fuzzy compensator without the need for any mathematical modeling of the plant. The difficulty of fine-tuning the scale factors and formulating the correct control rules in a basic fuzzy controller may be reduced using the proposed scheme. The scheme is applied to the control speed of a wound rotor induction motor process. The control system is designed to maintain efficiency of motor and compensate power factor of system. That is: the proposed controller gives the controlled system by keeping the speed constant and the good transient response without overshoot can be obtained.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.9A
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• pp.1332-1339
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• 2000

This paper presents the architecture and design of a high speed asymmetric data transmission baseband MODEM ASIC chip for CATV networks. The implemented MODEM chip supports the physical layer of the DOCSIS(Data Over Cable Service Interface Specification) standard in MCNS(Multimedia Cable Network System) The chip consists of a QPSK/16-QAM transmitter and a 64/256-QAM receiver which contain a symbol timing recovery circuit, a carrier recovery circuit, a blind equalizer using MMA and LMS algorithms. The chip can support data rates of 64Mbps at 256 QAM and 48Mbps at 64-QAM and can provide symbol rates up to 8MBaud. This symbol rate is faster than existing QAM receivers. We have performed logic synthesis using the $0.35\mu\textrm{m}$ standard cell library. The total number of gates is about 290,000 and the implemented chip is being fabricated and will be delivered soon.

• Nuclear Engineering and Technology
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• v.47 no.4
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• pp.443-453
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• 2015

A hybrid safety injection tank (H-SIT) can enhance the capability of an advanced power reactor plus (APR+) during a station black out (SBO) that is accompanied by a severe accident. It may a useful alternative to an electric motor. The operations strategy of the H-SIT has to be investigated to achieve maximum utilization of its function. In this study, the master logic diagram (i.e., an analysis for identifying the differences between an H-SIT and a safety injection pump) and an accident case classification were used to determine the parameters of the H-SIT operation. The conditions that require the use of an H-SIT were determined using a decision-making process. The proper timing for using an H-SIT was also analyzed by using the Multi-dimensional Analysis of Reactor Safety (MARS) 1.3 code (Korea Atomic Energy Research Institute, Daejeon, South Korea). The operation strategy analysis indicates that a H-SIT can mitigate five types of failure: (1) failure of the safety injection pump, (2) failure of the passive auxiliary feedwater system, (3) failure of the depressurization system, (4) failure of the shutdown cooling pump (SCP), and (5) failure of the recirculation system. The results of the MARS code demonstrate that the time allowed for recovery can be extended when using an H-SIT, compared with the same situation in which an H-SIT is not used. Based on the results, the use of an H-SIT is recommended, especially after the pilot-operated safety relief valve (POSRV) is opened.

• Journal of the Semiconductor & Display Technology
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• v.6 no.1 s.18
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• pp.53-57
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• 2007

In this paper, the intelligent estimation algorithm is developed for residual quantity estimate of lithium secondary cell and we suggest the control algorithm to get battery SOC through thermal modeling of electric cell. Lithium secondary cell gives cycle life, charge characteristic, discharge characteristic, temperature characteristic, self-discharge characteristic and the capacity recovery rate etc. Therefore, we make an accurate estimate of the capacity of battery according to thermal modeling to know the capacity of electric cell that is decreased by various special quality of lithium secondary cell. And we show effectiveness through comparison of value as result that use simulation and fuzzy logic.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.285-291
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• 2001

An 8-b$\times$8-b adiabatic pipelined multiplier is designed. Simplified four phase clock generator is also designed to provide supply clocks for adiabatic circuits. All the clock line charge on the capacitive interconnections is recovered to save energy. Adiabatic circuits are designed based on ECRL(efficient charge recovery logic) and are integrated using 0.6${\mu}{\textrm}{m}$ CMOS technology. The efficiency of proposed supply clock generator is better than the previous one by 4~11%. Simulation results show that the power consumption of adiabatic pipelined multiplier is reduced by a factor of 2.6~3.5 compared to a conventional pipelined CMOS multiplier.

• Transactions of the Korean hydrogen and new energy society
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• v.17 no.2
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• pp.133-140
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• 2006

The performance of proton exchange membrane fuel cell was decreased by reverse voltage using fuel starvation. Performance decrease in local area could be affected by duration and extent of reverse voltage. Hydrogen and air stoichiometic ratio was used to find the experimental condition of abrupt voltage decrease. LabVIEW was used to make control logic of automatic load off system in preset voltage. Reverse voltage experiment was done down to -1.2 V at constant current condition. When fuel cell voltage was reached to preset voltage, electronic load was disconnected to make open circuit voltage for 1 minute. Fuel cell performance was checked every 5 cycle and the degree of performance decrease and/or recovery was estimated. Ohmic resistance and charge transfer resistance were increased and platinum surface area was reduced 41% after reverse voltage experiment.

• Journal of the Korea Society of Computer and Information
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• v.23 no.1
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• pp.33-39
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• 2018

In this paper, We studied the possibility of SoC(System On Chip) design using infrared image processing IP(Intellectual Property). And, we studied NUC(Non Uniformity Correction), BPR(Bad Pixel Recovery), and CEM(Contrast Enhancement) processing, the infrared image processing algorithm implemented by IP. We showed the logic and timing diagram implemented through the hardware block designed based on each algorithm. Each algorithm was coded as RTL(Register Transfer Level) using Verilog HDL(Hardware Description Language), ALTERA QUARTUS synthesis, and programed in FPGA(Field Programmable Gated Array). In addition, we have verified that the image data is processed at each algorithm without any problems by integrating the infrared image processing algorithm. Particularly, using the directly manufactured electronic board, Processor, SRAM, and FLASH are interconnected and tested and the verification result is presented so that the SoC type can be realized later. The infrared image processing IP proposed and verified in this study is expected to be of high value in the future SoC semiconductor fabrication. In addition, we have laid the basis for future application in the camera SoC industry.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2341-2347
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• 2016

In this paper, we implement monitoring system for grain sorting using a high-speed FPGA and embedded LINUX. The proposed system is designed by base on web server and web-based applications while existing system was designed by base on stand-alone mode.The interface the Web server with high speed hardware of FPGA is designed on the implemented monitoring system. The proposed system has the advantages of multi-tasking on Linux web server and real-time high speed on FPGA also. The control logic of a high speed rate line-scan CCD camera, the method of center of gravity, HSL decoding and the interface on the Web server are implemented in FPGA. The implemented monitoring system has the advantage of being able to control the grain monitoring, system failure and recovery remotely by web application. As a result, we can upgrade the performance of sorting quality compared by existing system.