• Journal of the Korea Society of Computer and Information
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• v.14 no.7
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• pp.65-72
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• 2009

This paper proposed VCR cryptographic algorithm that adapted in TCP/IP protocol architecture and wire/wireless communication network environments. we implemented by hardware chip level because proposed VCR cryptographic algorithm perform scalable & reconfigurable operations into the security system. Proposed VCR cryptographic algorithm strengthens security vulnerability of TCP/IP protocol and is very profitable real-time processing and encipherment of high-capacity data and multi-user communication because there is important purpose to keep security about many user as that have variable round numbers function in network environments.

• The KIPS Transactions:PartC
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• v.11C no.7 s.96
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• pp.951-958
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• 2004

Nowadays NGN is developed for supporting the e-Commerce, Internet trading, e-Government, e-mail, virtual-life and multimedia. Internet gives us the benefit of remote access to the information but causes the attacks that can break server and modify information. Since 2000 Nimda, Code Red Virus and DSoS attacks are spreaded in Internet. This attack programs make tremendous traffic packets on the Internet. In this paper, we designed and developed the Bandwidth Controller in the gateway systems against the bandwidth saturation attacks. This Bandwidth con-troller is implemented in hardware chipset(FPGA) Virtex II Pro which is produced by Xilinx and acts as a policing function. We reference the TBF(Token Bucket Filter) in Linux Kernel 2.4 and implemented this function in HDL(Hardware Description Language) Verilog. This HDL code is synthesized in hardware chipset and performs the gigabit traffic in real time. This policing function can throttle the traffic at the rate of band width controlling policy in bps speed.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.459-466
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• 2002

Modern embedded system employs a hybrid architecture which contains a general micro processor and reconfigurable devices such as FPGAS to retain flexibility and to meet timing constraints. It is a hard and important problem for embedded system designers to explore and find a right system configuration, which is known as design space exploration (DSE). With DES, it is possible to predict a final system configuration during the design phase before physical implementation. In this paper, we implement a timing analysis simulator for a DSE on a hybrid embedded system. The simulator, integrating exiting timing analysis tools for hardware and software, is designed by extending Y-chart approach, which allows quantitative performance analysis by varying design parameters. This timing analysis simulator is expected to reduce design time and costs and be used as a core module of a DSE for a hybrid embedded system.

• Journal of the Korean Institute of Intelligent Systems
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• v.9 no.6
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• pp.634-643
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• 1999

This paper concerns an implementation of f~rry logic controller (FLC') on a reconfigurahle FP

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.667-670
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• 2004

In this paper, we have presented the improved IF transceiver architecture and the implementation and experimental results on re-configurable transceiver based on digital IF for multiple wideband OFDM/TDD base stations for high-speed portable internet-service in which is issued Korea. The implemented IF transceiver has been designed to support multiple frequency allocations and multiple standards by only modifying the programmable software not its hardware like as the software-defined-radio concept. Also, the digital complex quadrature modulation technique has been used for the digital IF transmitter, which is able to combine multiple frequency bands in digital processing block not RF block and to reject the image frequency signals. And the bandpass sampling technique has been used for the digital IF receiver to reduce the sampling rate of ADC. This paper has shown the experiment results on the frequency response and constellation on the base-station implemented using the modified IEEE 802.16a/e physical layer channel structure based on OFDM/TDD.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.163-165
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• 2014

In this paper, we propose a world's first programmable video processing platform for video quality enhancement of 8K ($7680{\times}4320$) UHD (Ultra High Definition) TV at 60 frames per second. To support huge computation and memory bandwidth of video quality enhancement for 8K resolution, the proposed platform has unique features like symmetric multi-cluster architecture for data partitioning, ring data-path between clusters to support data pipelining, on-the-fly processing architecture to reduce DDR bandwidth, flexible hardware to accelerating common kernel in video enhancement algorithms. In addition to those features, general programmability of SRP (Samsung reconfigurable processor) as main core of the proposed platform makes it possible to upgrade continuously video enhancement algorithm even after the platform is fixed. This ability is very important because algorithms for 8K DTV is under development. The proposed sub-system has been embedded into SoC (System on Chip) and new 8K UHD TV using the programmable SoC is expected at CES2015 for the first time in the world.

• Journal of Digital Contents Society
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• v.10 no.4
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• pp.605-614
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• 2009

The software-defined radio (SDR) is a radio communication technology that can reconfigure necessary application software on a common hardware platform to deal with several kind of radio communication environment. It is necessary for a system that can control and analyze functionalities of a system in order to verify the SCA-based reconfigurable middleware platform, SCARLET that implements the SDR technology. In this paper, we propose and implement the architecture of the waveform manager that is connected with SCARLET and performs management and control functionalities. We verify the performance of the waveform manager by testing each functionality of the overall system that uses the SCARLET middleware platform.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.6
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• pp.539-545
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• 2011

This paper describes an intelligent service robot system for managing a store in an unmanned environment. The robot can be a good replacement for humans because it is possible to work all day and to remember lots of information. We design a system architecture for configuring many intelligent functions of intelligent service robot system which consists of four layers; a User Interaction Layer, a Behavior Scheduling Layer, a Intelligent Module Layer, and a Hardware Layer. We develop an intelligent service robot 'Part Timer' based on the designed system architecture. The 'Part Timer' has many intelligent function modules such as face detection-recognition-tracking module, speech recognition module, navigation module, manipulator module, appliance control module, etc. The 'Part Timer' is possible to answer the phone and this function gives convenient interface to users.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.1
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• pp.153-160
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• 1996

In this paper, we propose an efficient digital architecture for the discrete-time cellular neural networks (DTCNN's). DTCNN's have the locality and the translation invariance in the templates which determine the patterns of the connection between the cells. Using distributed arithmetic (DA) and the characteristics of DTCNN, we propose a simple implementation of DTCNN. The bus width in the cell-to-cell interconnection is reduced to one bit because of DA's bitwise operation. We implemented the reconfigurable architecture of DTCNN using programmable FPGA.

• Journal of the Korea Society of Computer and Information
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• v.13 no.6
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• pp.195-201
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• 2008

We proposed that is suitable network environment and wire/wireless communication network, easy of implementation, security level preservation, scalable & reconfigurable to TCP/IP protocol architecture to implement suitable smart card MS-Serpent cryptographic algorithm for smart card by hardware base chip level that software base is not implement. Implemented MT-Serpent cryptosystem have 4,032 in gate counter and 406.2Mbps@2.44MHz in throughput. Implemented MS-Serpent cryptographic algorithm strengthens security vulnerability of TCP/IP protocol to do to rescue characteristic of smart card and though several kind of services are available and keep security about many user in wire/wireless environment, there is important purpose.