• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.1355-1360
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• 2005

In this paper, we approach the problem of image filter design automation using a kind of intrinsic evolvable hardware architecture. For the purpose of implementing the intrinsic evolution process in a common FPGA chip and evolving a complicated digital circuit system-image filter, the design automation system employs the reconfigurable circuit architecture as the reconfigurable component of the EHW. The reconfigurable circuit architecture is inspired by the Cartesian Genetic Programming and the functional level evolution. To increase the speed of the hardware evolution, the whole evolvable hardware system which consists of evolution algorithm unit, fitness value calculation unit and reconfigurable unit are implemented by a commercial FPGA chip. The Celoxica RC1000 card which is fitted with a Xilinx Virtex xcv2000E FPGA chip is employed as the experiment platform. As the result, we conclude the terms of the synthesis report of the image filter design automation system and hardware evolution speed in the Celoxica RC1000 card. The evolved image filter is also compared with the conventional image filter form the point of filtered image quality.

• 한국전자파학회논문지
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• 제21권4호
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• pp.381-391
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• 2010

본 논문에서는 상용 초고주파 MEMS 스위치를 이용하여 세 개의 주파수 대역에서 재구성 동작이 가능한 주파수 재구성 능동 배열 안테나 시스템(Reconfigurable Active Array Antenna System: RAA System)을 제안하였다. MEMS 스위치는 삽입 손실 및 선형성 특성이 우수하고 격리도가 높아 주파수 재구성 시스템 구현 시, 재구성을 위한 스위치로 인한 성능 열화가 거의 없다는 장점이 있다. 제안된 주파수 재구성 능동 배열 안테나 시스템은 간단한 구조의 임피던스 매칭 회로(Reconfigurable impedance Matching Circuit: RMC)를 갖는 주파수 재구성 증폭기(Reconfigurable Front-end Amplifier: RFA)가 집적화 되어 있으며, 안테나 방사체(Reconfigurable Antenna Element: RAE)와 재구성 제어 보드(Reconfiguration Control Board: RCB)로 구성되어 있다. 본 논문에서 제안한 RAA 시스템은 850 MHz, 1.9 GHz, 3.4 GHz의 세 개 주파수로 재구성되어 동작하며, 안테나 방사체는 $2{\times}2$ 배열을 가지고 각각의 방사체는 광대역 다이폴 형태를 갖는다. 제작된 RAA 시스템은 실험을 통하여 그 타당성을 확인하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1061-1064
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• 1998

This paper proposes a new topology-based partition method for reconfigurable FPGA systems whose components nd the number of interconnections are predetermined. Here, the partition problem must also consider nets that pass through components such as FPGAs and routing devices to route 100%. We formulate it as a quadratic boolean programming problem suggest a paritition method for it. Experimental results show 100% routing, and up to 15% improvement in the maximum number of I/O pins.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.199-204
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• 2003

This paper proposes reconfigurable hardware structures for spreading and scrambling of multi-mode CDMA systems. The proposed reconfigurable structures supporting IS-95, cdma2000 and WCDMA, include a pseudo noise code generator, a channelization code generator and a control circuit for signal flow control. The proposed reconfigurable structures provide an efficient hardware usage for multi-mode CDMA systems. The synthesis results show the area reduction about 24.7% compared with the original code generators. The proposed structures can provide efficient reconfigurability and high speed operations for future SDR systems.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.294-301
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• 2017

This paper presents a low power ${\Sigma}{\Delta}$ modulator for an implantable chip to acquire a bio-signal such as EEG, DBS, and EMG. In order to reduce a power consumption of the proposed fourth order modulator, two op-amps utilized for the first two integrators are reconfigured to drive the second two integrators. The KT/C noise reduction circuit in the first two integrators is employed to enhance SNR of the modulator. The proposed circuit was fabricated in a 0.18 um CMOS n-well 1 poly 6 metal process with the active chip core area of $900um{\times}800um$ and the power consumption of 830 uW. Measurement results were demonstrated to be SNDR of 76 dB, DR of 77 dB, ENOB of 12.3 bit at the input frequency of 250 Hz and the clock frequency of 256 kHz. FOM1 and FOM2 were measured to be 41 pJ/step and 142.4 dB, respectively.

• 한국인터넷방송통신학회논문지
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• 제8권2호
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• pp.67-73
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• 2008

Reconfigurable radio technology is needed to reconstruct frequency and modem functionality, which can be different within various regions. In addition, it makes it possible for a single mobile handset to support various standards of wireless communication, and thus plays a key role inmobile convergence. A MMIC VCO(Monolithic Microwave Integrated Circuit Voltage Controlled Oscillator) has been developed to produce high power and wide bandwidth that adapts the Clapp-Gouriet type oscillator for series feedback. We were fabricated based on the 0.15um pHEMT from TRW. The MMIC VCO was connected to an alumina substrate on the carrier for testing. This MMIC VCO module shows good performance when compared with existing VCOs. Futhermore, it has potential as a reconfigurable MMIC VCO for ubiquitous communications such as LMDS (Local Multipoint Distribution Service), VSAT, Point to Point Radio and SATCOM.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.261-273
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• 2016

Reconfigurable finite impulse response (FIR) filters whose filter coefficients and filter order change dynamically during run-time play an important role in the software defined radio (SDR) systems, multi-channel filters, and digital up/down converters. However, there are not many reports on such reconfigurable designs which can support dynamic variation of filter order and filter coefficients. The purpose of this paper is to provide an architectural solution for the FIR filters to support run-time variation of the filter order and filter coefficients. First, two straightforward designs, namely, (i) single-MAC based design and (ii) full-parallel design are presented. For large variation of the filter order, two designs based on (iii) folded structure and (iv) fast FIR algorithm are presented. Finally, we propose (v) high throughput design which provides significant advantage in terms of hardware and/or time complexities over the other designs. We compare complexities of all the five structures, and provide the synthesis results for verification.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.405-414
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• 2016

IC-implementations provide high performance for solving the high computational cost of pattern matching but have relative low flexibility for satisfying different applications. In this paper, we report an associative memory architecture for k nearest neighbor (KNN) search, which is one of the most basic algorithms in pattern matching. The designed architecture features reconfigurable vector-component parallelism enabled by programmable switching circuits between vector components, and a dedicated majority vote circuit. In addition, the main time-consuming part of KNN is solved by a clock mapping concept based weighted frequency dividers that drastically reduce the in principle exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. A test chip in 180 nm CMOS technology, which has 32 rows, 8 parallel 8-bit vector-components in each row, consumes altogether in peak 61.4 mW and only 11.9 mW for nearest squared Euclidean distance search (at 45.58 MHz and 1.8 V).

• 한국정보처리학회논문지
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• 제6권11호
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• pp.2946-2953
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• 1999

Finite automation is a mathematical model to represent a system with discrete inputs and outputs. Finite automata are a useful tool for solving problems such as text editor, lexical analyzer, and switching circuit. In this paper, given a deterministic finite automaton of an input string of length n and m states, we propose a constant time parallel algorithm that represents the transition states of finite automata and determines the acceptance of an input string on a reconfigurable mesh of size [nm/2]$\times$2m.

• 한국전자파학회논문지
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• 제25권1호
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• pp.92-98
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• 2014

본 논문에서는 패치 배열과 그리드 구조를 응용하여 C-밴드인 7 GHz 대역에서 동작하는 재구성 주파수 선택 구조를 설계하였다. 본 논문에서 제안한 구조는 바랙터 다이오드를 이용하여 슬롯에서 발생하는 커패시턴스 변화로부터 주파수 재구성 특성을 얻었으며, 커패시턴스의 변화에 따른 투과 주파수의 변화를 구현하였다. 설계한 결과를 바탕으로 유연성을 갖는 FPCB(Flexible Printed Circuit Board)와 상용 바랙터 다이오드를 이용하여 재구성 주파수 선택 구조를 제작하고, 바이어스 전압의 변화에 따른 주파수 재구성 특성을 측정하였다. 제작된 재구성 주파수 선택 구조는 약 6.6~7.6 GHz의 광대역 주파수 재구성 특성(투과 주파수의 가변 범위)을 가지며, 본 논문에서 제안한 구조는 제한된 곡률에 대하여 유연성을 갖기 때문에, 항공기 또는 군함의 레이돔과 같은 곡면 형상 구조 중 완만한 곡면 구조에 적용이 용이하다.