• Journal of KIISE:Computing Practices and Letters
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• v.16 no.1
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• pp.17-22
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• 2010

As deployments of Flash memory are spreading out rapidly from tiny USB storages to large DB servers, interoperability become an indispensable requirement for Flash memory software architecture. For the purpose, many systems make use of the conventional FAT file system and FTL (Flash Translation Layer) software as a de facto standard. However, the tactless combination of the FAT file system and FTL does not satisfy diverse other requirements of a variety of systems. In this paper, we propose a novel reconfigurable integrated Flash memory software architecture, named INFLAWARE (INtegrated FLAsh softWARE) that supports not only interoperability but also reconfigurability and performance enhancement. Real implementation based experimental results have shown that INFLAWARE can achieve improvements of memory footprint up to 27% with an average of 19%, compared with the conventional FAT and FTL combination. Also, by using map_destroy technique, it can reduce response times of various applications up to 21% with an average of 10%.

• Journal of the Korea Institute of Military Science and Technology
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• v.26 no.1
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• pp.91-101
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• 2023

Modeling and Simulation(M&S) technology has been widely used to solve constraints such as time, space, safety, and cost when we implement the same development and test environments as real warfare environments to develop, test, and evaluate weapon systems for the last several decades. The integration and test environments employed for development and test & evaluation are required to provide Live Virtual Construction(LVC) simulation environments for carrying out requirement analysis, design, integration, test and verification. Additionally, they are needed to provide computing environments which are possible to reconfigure computing resources and software components easily according to test configuration changes, and to run legacy software components independently on specific hardware and software environments. In this paper, an Integration Test and Simulation for Engagement Control(ITSEC) bed using a bare-metal virtualization mechanism is proposed to meet the above test and simulation requirements, and it is applied and implemented for an air missile defense system. The engagement simulation experiment results conducted on air and missile defense environments demonstrate that the proposed bed is a sufficiently cost-effective and feasible solution to reconfigure and expand application software and computing resources in accordance with various integration and test environments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.401-407
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• 2016

We can consider the following problems for two given points p and q in a simple polygon P. (1) Compute the set of points of P which are visible from both p and q. (2) Compute the set of points of P which are visible from either p or q. They are corresponding to the problems which are to compute the intersection and the union of two visibility polygons. In this paper, we consider algorithms for solving these problems on a reconfigurable mesh(in short, RMESH). The algorithm in [1] can compute the intersection of two general polygons in constant time on an RMESH with size O($n^3$), where n is the total number of vertices of two polygons. In this paper, we construct the planar subdivision graph in constant time on an RMESH with size O($n^2$) using the properties of the visibility polygon for preprocessing. Then we present O($log^2n$) time algorithms for computing the union as well as the intersection of two visibility polygons, which improve the processor-time product from O($n^3$) to O($n^2log^2n$).

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.11
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• pp.1344-1352
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• 1999

본 논문에서는 두 단순 다각형의 교차 영역을 구하는 문제를 재구성메쉬(RMESH) 상에서 상수 시간에 해결하는 두 개의 알고리즘을 제시한다. 먼저, 두 다각형이 모두 볼록 다각형일 때, N$\times$N RMESH에서 상수 시간에 교차 영역을 구하는 알고리즘을 제시한다, 여기서 N은 두 다각형의 정점의 개수의 합이다. 그리고, 두 일반적인 단순 다각형의 교차 영역을 구하는 문제에 대해서 (N+T)$\times$(N+T)2 RMESH에서 수행되는 상수 시간 알고리즘을 제시한다, 여기서 T는 최악의 경우 두 다각형의 경계선 상의 교차점의 개수로서 두 다각형의 정점의 개수가 각각 n과 m일 때 n.m에 해당한다. 두 다각형 중 하나가 볼록 다각형인 경우는 T = 2.max{n, m}이다. 이 알고리즘은 두 다각형의 모든 교차 영역 조각들을 구한 후 RMESH의 0번째 열에 차례로 배치해 준다. Abstract In this paper, we consider two constant time algorithms for polygon intersection problems on a reconfigurable mesh(in short, RMESH). First, we present a constant time algorithm for computing the intersection of two convex polygons on an N$\times$N RMESH, where N is the total number of vertices in both polygons. Second, we present a constant time algorithm for computing the intersection of two simple polygons on an (N+T)$\times$(N+T)2 RMESH, where T is the worstcase number of intersection points between the boundaries of them. T = n m, where n and m are the numbers of vertices of two polygons respectively. If either of them is convex, then T = 2 max{n,m}. The algorithm computes the intersection of them, and then arranges each intersection component onto the 0-th column of the mesh.

• ETRI Journal
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• v.33 no.5
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• pp.731-740
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• 2011

Reconfigurable computing using a field-programmable gate-array (FPGA) device has become a promising solution in system design because of its power efficiency and design flexibility. To bring the benefit of FPGA to many application programmers, there has been intensive research about automatic translation from high-level programming languages (HLL) such as C and C++ into hardware. However, the large gap of syntaxes and semantics between hardware and software programming makes the translation challenging. In this paper, we introduce a new approach for the translation by using the widely used GCC compiler. By simply adding a hardware description language (HDL) backend to the existing state-of- the-art compiler, we could minimize an effort to implement the translator while supporting full features of HLL in the HLL-to-HDL translation and providing high performance. Our translator, called GCC2Verilog, was implemented as the GCC's cross compiler targeting at FPGAs instead of microprocessor architectures. Our experiment shows that we could achieve a speedup of up to 34 times and 17 times on average with 4-port memory over PICO microprocessor execution in selected EEMBC benchmarks.

• Journal of Korea Multimedia Society
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• v.7 no.10
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• pp.1400-1411
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• 2004

Recently, explosion of internet user requires fundamental changes on the architecture of Web service system, from single server system to clustered server system, in parallel with the effort for improving the scalability of the single internet server system. But current cluster-based server systems are dedicated to the single application, for example, One-IP server system. One-IP server system has a clustered computing node with the same function and tries to distribute each request based on the If to the clustered node evenly. In this paper, we implemented the more useful application service platform. It works on shared clustered server(back-end server) with an application server(front-end server) for a particular service. An application server provides a particular service at a low load by itself, but as the load increases, it reconfigures itself with one or more available server from the shared cluster and distributes the load on selected server evenly We used PVM for an effective management of the clustered server. We found the implemented application service platform provides more stable and scalable operation characteristics and has remarkable performance improvement on the dynamic load changes.

• Journal of Internet Computing and Services
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• v.5 no.2
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• pp.75-84
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• 2004

Geocasting, a variant of the conventional multicasting problem, is one of communication type in which the data packets are delivered to a group of all nodes within a specified geographical region (i.e., the geocasting region) and is called location-based multicasting(LBM)(l). An Ad-hoc network is a dynamically reconfigurable and temporary wireless network where all mobile devices using batteries as energy resources cooperatively maintain network connectivity without central administration or the assistance of base stations. Consequently, the technique to efficiently consume the limited amounts of energy resources is an important problem so that the system lifetime is maximized. In this paper, we propose a LBPA(Location-Based Power Aware) geocasting algorithm that selects energy-aware neighbor to route a packet towards the target region In Ad-hoc network environments. The method Is such that the energy consumption is balanced among the nodes in proportion to their energy reserves. Through the simulations, the proposed LBPA algorithm shows better results, that is, as good as 40% on the average over the conventional LBM algorithm in terms of the network lifetime.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.103-111
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• 2019

The IoT-driven large-scaled systems consist of connected things with on-chip executable embedded software. These light-weighted embedded things have limited hardware space, especially small size of on-chip flash memory. In addition, on-chip embedded software in flash memory is not easy to update in runtime to equip with latest services in IoT-driven applications. It is becoming important to develop light-weighted IoT devices with various software in the limited on-chip flash memory. The remote instruction execution in cloud via IoT connectivity enables to provide high performance software execution with unlimited software instruction in cloud and low-power streaming of instruction execution in IoT edge devices. In this paper, we propose a Cloud-IoT asymmetric structure for providing high performance instruction execution in cloud, still low power code executable thing in light-weighted IoT edge environment using remote instruction execution. We propose a simulated approach to determine efficient partitioning of software runtime in cloud and IoT edge. We evaluated the instruction cloudification using remote instruction by determining the execution time by the proposed structure. The cloud-connected instruction set simulator is newly introduced to emulate the behavior of the processor. Experimental results of the cloud-IoT connected software execution using remote instruction showed the feasibility of cloudification of on-chip code flash memory. The simulation environment for cloud-connected code execution successfully emulates architectural operations of on-chip flash memory in cloud so that the various software services in IoT can be accelerated and performed in low-power by cloudification of remote instruction execution. The execution time of the program is reduced by 50% and the memory space is reduced by 24% when the cloud-connected code execution is used.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.6
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• pp.850-858
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• 2022

To deploy Gate Recurrent Units (GRU) on resource-constrained embedded devices, this paper presents a reconfigurable FPGA-based GRU accelerator that enables structured compression. Firstly, a dense GRU model is significantly reduced in size by hybrid quantization and structured top-k pruning. Secondly, the energy consumption on external memory access is greatly reduced by the proposed reuse computing pattern. Finally, the accelerator can handle a structured sparse model that benefits from the algorithm-hardware co-design workflows. Moreover, inference tasks can be flexibly performed using all functional dimensions, sequence length, and number of layers. Implemented on the Intel DE1-SoC FPGA, the proposed accelerator achieves 45.01 GOPs in a structured sparse GRU network without batching. Compared to the implementation of CPU and GPU, low-cost FPGA accelerator achieves 57 and 30x improvements in latency, 300 and 23.44x improvements in energy efficiency, respectively. Thus, the proposed accelerator is utilized as an early study of real-time embedded applications, demonstrating the potential for further development in the future.

• Journal of Internet Computing and Services
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• v.9 no.5
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• pp.59-72
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• 2008

Computing systems in the modern era are expanding rapidly to include mobile-based businesses that make us of the various convergence distributed business process. This has lead to growing interest in the field of mobile embedded software development methodology, which has in turn lead to the proliferation of the embedded mobility. The use of CBD (Component Based Development) provides reusability, maintainability and portability, all of which are very important and focus issues to the business process. It also comes with the inherent productivity, quality and reliability of CBD. To make efficient use of CBD, though, clarified interface definitions for component integration are necessary. These definitions should be made up of collaborative hierarchical and horizontal architecture layers. Successful definitions should apply an effective framework made up of the architecture and process. In this paper, we describe an interface specification for small grained mobile embedded components(MEC) for the mobile embedded domain to meet maximum user requirements. We build and deploy the reconfigurable design patterns and components (in business domain categories) to make a component hierarchy and business logics for mobile embedded software. Proposed components specification plays a major role in development of the software for handling inconsistency in existing specification. It also includes plenty of specification information, using semantics and modeling based mechanisms to support business processes. We propose a development model of mobile embedded software using CBD for very complex and dynamic mobile business. We can apply it in a plug and play manner to develop the software. We verify that our framework supports very good productivity, quality and maintainability to meet the user's requirements in mobile business.