• Title/Summary/Keyword: Receiver front-end

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Design Considerations of K-band Front-End Module for Dynamic Range (Dynamic Range를 고려한 K-band Front-End Module 설계)

  • Han, Geon-Hee;Jang, Youn-Gil;Rhee, Young-Chul
    • The Journal of the Korea institute of electronic communication sciences
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    • v.7 no.1
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    • pp.15-20
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    • 2012
  • In this paper, we designed and analysed K-band front-end module for digital microwave communication system receiver which improvement of dynamic range. We also suggested method of minimum amplified input signal level used to minimize noise figure of low-noise amplifier for High dynamic range. The designed modules consist of active mixer with conversions gain and PL-DRO with high stability and quality factor. The designed modules performance is that has the characteristics of over 54dB conversion gain, 1.3dB noise figure.

A Differential Voltage-controlled Oscillator as a Single-balanced Mixer

  • Oh, Nam-Jin
    • International journal of advanced smart convergence
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    • v.10 no.1
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    • pp.12-23
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    • 2021
  • This paper proposes a low power radio frequency receiver front-end where, in a single stage, single-balanced mixer and voltage-controlled oscillator are stacked on top of low noise amplifier and re-use the dc current to reduce the power consumption. In the proposed topology, the voltage-controlled oscillator itself plays the dual role of oscillator and mixer by exploiting a series inductor-capacitor network. Using a 65 nm complementary metal oxide semiconductor technology, the proposed radio frequency front-end is designed and simulated. Oscillating at around 2.4 GHz frequency band, the voltage-controlled oscillator of the proposed radio frequency front-end achieves the phase noise of -72 dBc/Hz, -93 dBc/Hz, and -113 dBc/Hz at 10KHz, 100KHz, and 1 MHz offset frequency, respectively. The simulated voltage conversion gain is about 25 dB. The double-side band noise figure is -14.2 dB, -8.8 dB, and -7.3 dB at 100 KHz, 1 MHz and 10 MHz offset. The radio frequency front-end consumes only 96 ㎼ dc power from a 1-V supply.

Robustness Examination of Tracking Performance in the Presence of Ionospheric Scintillation Using Software GPS/SBAS Receiver

  • Kondo, Shun-Ichiro;Kubo, Nobuaki;Yasuda, Akio
    • Proceedings of the Korean Institute of Navigation and Port Research Conference
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    • v.2
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    • pp.235-240
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    • 2006
  • Ionospheric scintillation induces a rapid change in the amplitude and phase of radio wave signals. This is due to irregularities of electron density in the F-region of the ionosphere. It reduces the accuracy of both pseudorange and carrier phase measurements in GPS/satellite based Augmentation system (SBAS) receivers, and can cause loss of lock on the satellite signal. Scintillation is not as strong at mid-latitude regions such that positioning is not affected as much. Severe effects of scintillation occur mainly in a band approximately 20 degrees on either side of the magnetic equator and sometimes in the polar and auroral regions. Most scintillation occurs for a few hours after sunset during the peak years of the solar cycle. This paper focuses on estimation of the effects of ionospheric scintillation on GPS and SBAS signals using a software receiver. Software receivers have the advantage of flexibility over conventional receivers in examining performance. PC based receivers are especially effective in studying errors such as multipath and ionospheric scintillation. This is because it is possible to analyze IF signal data stored in host PC by the various processing algorithms. A L1 C/A software GPS receiver was developed consisting of a RF front-end module and a signal processing program on the PC. The RF front-end module consists of a down converter and a general purpose device for acquiring data. The signal processing program written in MATLAB implements signal acquisition, tracking, and pseudorange measurements. The receiver achieves standalone positioning with accuracy between 5 and 10 meters in 2drms. Typical phase locked loop (PLL) designs of GPS/SBAS receivers enable them to handle moderate amounts of scintillation. So the effects of ionospheric scintillation was estimated on the performance of GPS L1 C/A and SBAS receivers in terms of degradation of PLL accuracy considering the effect of various noise sources such as thermal noise jitter, ionospheric phase jitter and dynamic stress error.

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Optimization of Fixed-point Design on the Digital Front End in IEEE 802.16e OFDMA-TDD System (IEEE 802.16e OFDMA-TDD 시스템 Digital Front End의 Fixed-point 설계 최적화)

  • Kang Seung-Won;Sun Tae-Hyoung;Chang Kyung-Hi;Lim In-Gi;Eo Ik-Soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.7C
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    • pp.735-742
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    • 2006
  • In this paper, we explain the operation scheme and fixed-point design method of DFE (Digital Front End), which performs DC offset compensation, automatic frequency control, and automatic gain control over the input signal to the UE (User Equipment) receiver of IEEE 802.16e OFDMA-TDD system. Then, we analyze the performance of DFE under ITU-R M. 1225 Veh-A 60km/h channel environment. To optimize the fixed-point design of DFE, we reduce the number of bit resulted from calculation without performance degradation, leading to the decreased complexity of the operation in H/W, and design the Loop filter with considering trade-off between the Acquisition time and the Stability.

Design of Variable Gain Receiver Front-end with Wide Gain Variable Range and Low Power Consumption for 5.25 GHz (5.25 GHz에서 넓은 이득 제어 범위를 갖는 저전력 가변 이득 프론트-엔드 설계)

  • Ahn, Young-Bin;Jeong, Ji-Chai
    • Journal of IKEEE
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    • v.14 no.4
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    • pp.257-262
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    • 2010
  • We design a CMOS front-end with wide variable gain and low power consumption for 5.25 GHz band. To obtain wide variable gain range, a p-type metal-oxide-semiconductor field-effect transistor (PMOS FET) in the low noise amplifier (LNA) section is connected in parallel. For a mixer, single balanced and folded structure is employed for low power consumption. Using this structure, the bias currents of the transconductance and switching stages in the mixer can be separated without using current bleeding path. The proposed front-end has a maximum gain of 33.2 dB with a variable gain range of 17 dB. The noise figure and third-order input intercept point (IIP3) are 4.8 dB and -8.5 dBm, respectively. For this operation, the proposed front-end consumes 7.1 mW at high gain mode, and 2.6 mW at low gain mode. The simulation results are performed using Cadence RF spectre with the Taiwan Semiconductor Manufacturing Company (TSMC) $0.18\;{\mu}m$ CMOS technology.)

THE DEVELOPMENT OF A LOW NOISE 230 GHZ SIS RECEIVER IN NAGOYA UNIVERSITY

  • XIAO K. C.;OGAWA H.;FUKUI Y.;SUZUKI H.
    • Journal of The Korean Astronomical Society
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    • v.29 no.spc1
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    • pp.413-414
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    • 1996
  • A 230 GHz SIS tunnel junction receiver has been being developed for radio astronomy in Nagoya University. In this heterodyne receiver, we use a $\~$1/3 reduced hight rectangular waveguide SIS mixer with two tuning elements as front end. The mixer block with SIS junction was cooled to 4K with a closed cycle He-gas refrigerator. So far, a double sideband receiver noise temperature lower than l00K in 222-237 GHz is obtained. The receiver exhibits a best DSB noise temperature of 69K at 236 GHz as well as 228 GHz.

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An Oscillator and a Mixer for 140-GHz Heterodyne Receiver Front-End based on SiGe HBT Technology

  • Yoon, Daekeun;Song, Kiryong;Kaynak, Mehmet;Tillack, Bernd;Rieh, Jae-Sung
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.1
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    • pp.29-34
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    • 2015
  • This paper reports a couple of key circuit blocks developed for heterodyne receiver front-ends operating near 140 GHz based on SiGe HBT technology. Firstly, a 123-GHz oscillator was developed based on Colpitts topology, which showed -5 dBm output power and phase noise of -107.34 dBc/Hz at 10 MHz. DC power dissipation was 25.6 mW. Secondly, a 135 GHz mixer was developed based on a modified Gilbert Cell topology, which exhibited a peak conversion gain of 3.6 dB at 1 GHz IF at fixed LO frequency of 134 GHz. DC power dissipation was 3 mW, which mostly comes from the buffer.

Design of the RF Front-end for L1/L2 Dual-Band GPS Receiver (L1/L2 이중-밴드 GPS 수신기용 RF 전단부 설계)

  • Kim, Hyeon-Deok;Oh, Tae-Soo;Jeon, Jae-Wan;Kim, Seong-Kyun;Kim, Byung-Sung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.10
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    • pp.1169-1176
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    • 2010
  • The RF front-end for L1/L2 dual-band Global Positioning System(GPS) receiver is presented in this paper. The RF front-end(down-converter) using low IF architecture consists of a wideband low noise amplifier(LNA), a current mode logic(CML) frequency divider and a I/Q down-conversion mixer with a poly-phase filter for image rejection. The current bleeding technique is used in the LNA and mixer to obtain the high gain and solve the head-room problem. The common drain feedback is adopted for low noise amplifier to achieve the wideband input matching without inductors. The fabricated RF front-end using $0.18{\mu}m$ CMOS process shows a gain of 38 dB for L1 and 41 dB for L2 band. The measured IIP3 is -29 dBm in L1 band and -33 dBm in L2 band, The input return loss is less than -10 dB from 50 MHz to 3 GHz. The measured noise figure(NF) is 3.81 dB for L1 band and 3.71 dB for L2 band. The image rejection ratio is 36.5 dB. The chip size of RF front end is $1.2{\times}1.35mm^2$.

H-Band(220~325 GHz) Transmitter and Receiver for an 1.485 Gbit/s Video Signal Transmission (H-대역(220~325 GHz) 주파수를 이용한 1.485 Gbps 비디오 신호 전송 송수신기)

  • Chung, Tae-Jin;Lee, Won-Hui
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.3
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    • pp.345-353
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    • 2011
  • An 1.485 Gbit/s video signal transmission system using the carrier frequency of H-band(220~325 GHz) was implemented and demonstrated for the first in domestic. The RF front-end was composed of Schottky barrier diode sub-harmonic mixers(SHM) and frequency triplers, and diagonal horn antennas for transmitter and receiver, respectively. The transmitted carrier frequency of 246 GHz was implemented in the H-band, and LO frequencies of H-band SHM is 120 GHz and 126 GHz for transmit and receive chains, respectively. The modulation scheme is ASK(Amplitude Shift Keying) where IF frequency is 5.94 GHz and the envelop detection was used in heterodyne receiver architecture, and direct detection receiver using ZBD(Zero Bias Detector) was implemented as well. The 1.485 Gbit/s video signal with HD-SDI format was successfully transmitted over wireless link distance of 5 m and displayed on HDTV at the transmitted average output power of 20 ${\mu}W$.

Design of A 3V CMOS Programmable Gain Amplifier for the Information Signal Processing System (정보처리 시스템용 3V CMOS 프로그래머블 이득 증폭기 설계)

  • 송제호;김환용
    • Journal of Korea Multimedia Society
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    • v.5 no.6
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    • pp.753-758
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    • 2002
  • In this paper, low voltage 3V CMOS programmable gain amplifier(PGA) for using in the transmitter and receiver of ADSL analog front-end is designed. The designed receive PGA is connected with 1.1MHz continuous lowpass fillet and controls the gain from 0dB to 30dB. And also the transmitter PGA is connected with 138KHz lowpass filter and controls the gain from -15dB to 0dB. The gain of All PGAs can be programmed by digital logic circuits and main controller. The designed PGAs are verified using HSPICE simulation with $0.35\mu{m}$ CMOS parameter.

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