• 한국군사과학기술학회지
• /
• 제14권5호
• /
• pp.825-832
• /
• 2011

In this paper, we described the design and measurement results of a Front-End Receiver for S-band active phased array radar. The Front-End Receiver has input P1dB of -4dBm and IIP3 of 7dBm. The measurement results show that gain is $24{\pm}0.7dB$, noise figure are less than 2.3dB over the frequency range of $fc{\pm}0.2GHz$. The Front-End Receiver can protect the receiver path from large input signals with a maximum peak power of multi-kW and recovery time is less than 0.8us. The measurement results satisfy all specifications.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
• /
• pp.894-897
• /
• 2003

Recently, the rapid growth of mobile radio system has led to an increasing demand of low-cost high performance communication IC's. In this paper, we have designed RF front end for wireless LAN receiver employ zero-IF architecture. A low-noise amplifier (LNA) and double-balanced mixer is included in a front end. The zero-IF architecture is easy to integrate and good for low power consumption, so that is coincided to requirement of wireless LAN. But the zero-IF architecture has a serious problem of large offset. Image-reject mixer is a good structure to solve offset problem. Using offset compensation circuit is good structure, too. The front end is implemented in 0.25 ${\mu}m$ CMOS technology. The front end has a noise figure of 5.6 dB, a power consumption of 16 mW and total gain of 22 dB.

• 한국정보통신학회논문지
• /
• 제13권11호
• /
• pp.2267-2272
• /
• 2009

본 논문에서는 다층형 결합 선로를 이용한 6-단자 위상 상관기와 동일한 구조를 갖는 반송파 복원기 그리고 위상 변위기를 갖는 일원화된 6-단자 직접변환 수신 전처리부를 설계 제작한다. 전력 분배기와 하이브리드 결합기로 구성되는 6-단자 소자는 다층형 결합 선로 구조로 이루어지며, 수신부 위상 상관기와 반송파 복원기 그리고 위상 변위기의 기본 구조 요소로 작용한다. 다층형 결합 선로 구조로 구성되는 일원화된 수신 전처리부는 구성이 간단하고 집적화가 용이하다. 설계 제작된 다층형 결합 구조 6-단자 수신 전처리부는 일정한 반송파 신호를 재생하고, PSK 전송 신호를 복원한다.

• Journal of electromagnetic engineering and science
• /
• 제8권1호
• /
• pp.34-39
• /
• 2008

An RF front-end dual-conversion receiver for $3{\sim}5\;GHz$ MB-OFDM UWB systems is implemented in $0.18\;{\mu}m$ CMOS technology. The receiver includes a two-stage UWB LNA, an RF mixer, an IF I/Q mixer, and a frequency synthesizer. The proposed receiver adopts the dual-conversion architecture to mitigate the burden of design of the frequency synthesizer. Accordingly, the proposed frequency synthesizer generates four LO tones from only one VCO. The receiver front-end achieves power gain of 16.3 to 21 dB, NF of 7 to 7.6 dB over $3{\sim}5\;GHz$, and IIP3 of -21 dBm, while consuming 190 mW from a 1.8 V supply.

• Journal of Positioning, Navigation, and Timing
• /
• 제6권1호
• /
• pp.1-8
• /
• 2017

In this study, to design a multi-GNSS receiver using single RF front-end, the receiving performances for various frequency plans were evaluated. For the fair evaluation and comparison of different frequency plans, the same signal needs to be received at the same time. For this purpose, two synchronized RF front-ends were configured using USRP X310, and PC-based software was implemented so that the quality of the digital IF signal received at each front-end could be evaluated. The software consisted of USRP control, signal reception, signal acquisition, signal tracking, and C/N0 estimation function. Using the implemented software and USRP-based hardware, the signal receiving performances for various frequency plans, such as the signal attenuation status, overlapping of different systems, and the use of imaginary or real signal, were evaluated based on the C/N0 value. The results of the receiving performance measurement for the various frequency plans suggested in this study would be useful reference data for the design of a multi-GNSS receiver in the future.

• 한국해양공학회지
• /
• 제24권1호
• /
• pp.166-171
• /
• 2010

In this paper, the front-end of a digital receiver with a 25 kHz carrier frequency, 5 kHz symbol rate, and any excess-bandwidth is designed using two basic facts. The first is known as the uniform sampling theorem, which states that the sampled sequence might not suffer from aliasing even if its sampling rate is lower than the Nyquist sampling rate if the analog signal is a bandpass one. The other fact is that if the sampling rate is 4 times the center frequency of the sampled sequence, the front-end processing complexity can be dramatically reduced due to the half of the sampled sequence to be multiplied by zero in the demixing process. Furthermore, the designed front-end is simplified by introducing sub-filters and sub-sampling sequences. The designed front-end is composed of an A/D converter, which takes samples of a bandpass filtered signal at a 20 kHz rate; a serial-to-parallel converter, which converts a sampled bandpass sequence to 4 parallel sub-sample sequences; 4 sub-filter blocks, which act as a frequency shifter and lowpass filter for a complex sequence; 4 synchronized switches; and 2 adders. The designed front-end dramatically reduces the computational complexity by more than 50% for frequency shifting and lowpass filtering operations since a conventional front-end requires a frequency shifting and two lowpass filtering operations to get one lowpass complex sample, while the proposed front-end requires only four filtering operation to get four lowpass complex samples, which is equivalent to one filtering operation for one sample.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제11권1호
• /
• pp.59-64
• /
• 2011

A low noise and low power RF front-end for 5.8 GHz DSRC (Dedicated Short Range Communication) receiver is presented. The RF front-end is composed of a single-to-differential two-stage LNA and a Gilbert down-conversion mixer. In order to remove an external balun and 5.8 GHz LC load tuning circuit, a single-to-differential LNA with capacitive cross coupled pair is proposed. The RF front-end is fabricated in a 0.13 ${\mu}m$ CMOS process and draws 7.3 mA from a 1.2 V supply voltage. It shows a voltage gain of 40 dB and a noise figure (NF) lower than 4.5 dB over the entire DSRC band.

• 한국ITS학회:학술대회논문집
• /
• 한국ITS학회 2008년도 제7회 추계학술대회 및 정기총회
• /
• pp.380-382
• /
• 2008

• ETRI Journal
• /
• 제42권6호
• /
• pp.943-950
• /
• 2020

We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2008년도 하계종합학술대회
• /
• pp.421-422
• /
• 2008

In this paper, CMOS RF front-end circuits for an L1/L5 dual-band global positioning system (GPS)/Galileo receiver are designed in $0.13\;{\mu}m$ CMOS technology. The RF front-end circuits are composed of an RF single-to-differential low noise amplifier, an RF polyphase filter, two down-conversion mixers, two transimpedance amplifiers, a IF polyphase filter, four de-coupling capacitors. The CMOS RF front-end circuits provide gains of 43 dB and 44 dB, noise figures of 4 dB and 3 dB and consume 3.6 mW and 4.8 mW from 1.2 V supply voltage for L1 and L5, respectively.