• 한국산업정보학회논문지
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• 제18권2호
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• pp.35-40
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• 2013

본 논문에서 높은 주파수 LO 신호와 낮은 주파수 LO신호를 동시에 사용하는 새로운 구조의 이미지 제거 수신기 구조를 제안하였다. 제안된 구조는 기존의 하나의 LO 신호를 사용하는 경우보다 저 잡음 지수 성능과 높은 선형성 특성을 갖는다. 또한 제안된 수신기는 기존의 Weaver 이미지 제거 수신기 구조 보다 같은 이득 error와 위상 error가 존재할 때도 6dB 이상의 높은 이미지 제거 특성을 보인다. 제안된 수신기 구조의 특성을 증명하기 위하여 이득 및 위상 error가 존재할 때의 이미지 제거 특성 공식을 유도하였다. 그리고 이 공식의 유용성을 시스템 시뮬레이션을 통하여 증명하였다. 따라서 높은 이미지 제거 특성 때문에 제안된 새로운 수신기 구조가 이미지 제거 수신기로써 널리 사용이 가능할 것으로 기대한다.

• 대한전자공학회논문지TC
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• 제47권8호
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• pp.24-31
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• 2010

본 논문에서는 IEEE 802.15.4a chirp spread spectrum (CSS) 를 위한 저복잡도 수신기 구조를 제안한다. 무선 통신 시스템에서는 일반적으로 수신기의 신호 수신시 최대 SNR (Signal to Noise power Ratio) 을 보장하는 정합필터를 사용하여 신호를 복조를 하는 것이 일반적이다. 하지만, 정합필터는 하드웨어 복잡도가 높아 저복잡도, 저가격의 센서 네트워크를 목적으로 하는 CSS에서는 적합하지 않다. 따라서 본 논문에서는 정합필터를 사용하지 않고 인접 심볼 간 차등 곱셈과 누적을 통하여 chirp 신호를 복조하는 새로운 수신기 구조를 제안한다. 또한, CSS에 사용되는 이원 직교 코드의 특성을 이용하여 곱셈기를 사용하지 않은 이원 직교 디코더 구조를 제안한다. 제안하는 수신기 구조는 정합필터 기반 구조에 비하여 BER (Bit Error Rate) 성능은 떨어지지만 하드웨어 구현을 위한 곱셈기, 가/감산기, 레지스터 등의 자원의 수를 절감하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권4호
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• pp.277-282
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• 2008

A fully integrated inductorless CMOS impulse radio ultra-wideband (IR-UWB) receiver is implemented using $0.18\;{\mu}m$ CMOS technology for 3-5 GHz application. The UWB receiver adopts the non-coherent architecture, which removes the complexity of RF architecture and reduces power consumption. The receiver consists of inductorless differential three stage LNA, envelope detector, variable gain amplifier (VGA), and comparator. The measured sensitivity is -70 dBm in the condition of 5 Mbps and BER of $10^{-3}$. The receiver chip size is only $1.8\;mm\;{\times}\;0.9\;mm$. The consumed current is 15 mA with 1.8 V supply.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 2002년도 정기총회 및 학술대회
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• pp.9-14
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• 2002

Direct-conversion receiver(DCR) architecture has superior advantages in size, cost, and power over superheterodyne receiver architectures. However, the use of direct-conversion receiver architecture has been limited due to the direct-current offset noise. The ac coupling, which is used to overcome the direct-current offset noise, causes an inter-symbol interference(ISI), whose effects can be effectively mitigated using an equalizer. In this paper, the performance of a direct-conversion receiver with ac coupling in the presence of direct-current offset is analyzed via computer simulation. The simulation result shows that by using decision feedback equalizer with LMS(Least Mean Square) algorithm, signal-to-noise ratio loss of the direct-conversion receiver compared to the idea receiver can be reduced to less than 1㏈ for corner frequencies as large as 10% of the symbol rate.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권1호
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• pp.6-14
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• 2011

This paper presents a high-speed QR decomposition architecture for the multi-input-multi-output (MIMO) receiver based on Givens rotation. Under fast-varying channel, since the inverse matrix calculation has to be performed frequently in MIMO receiver, a high performance and low latency QR decomposition module is highly required. The proposed QR decomposition architecture is composed of Sign-Select Lookahead (SSL) coordinate rotation digital computer (CORDIC). In the SSL-CORDIC, the sign bits, which are computed ahead to select which direction to rotate, are used to select one of the last iteration results, therefore, the data dependencies on the previous iterations are efficiently removed. Our proposed QR decomposition module is implemented using TSMC 0.25 ${\mu}M$ CMOS process. Experimental results show that the proposed QR architecture achieves 34.83% speed-up over the Compact CORDIC based architecture for the 4 ${\times}$ 4 matrix decomposition.

• Journal of electromagnetic engineering and science
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• 제8권2호
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• pp.76-83
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• 2008

A low power(9 mW) highly-digitized 2.4 GHz receiver for sensor network applications(IEEE 802.15.4 LR-WPAN) is realized by a $0.18{\mu}m$ CMOS process. We adopted a novel receiver architecture adding an intermediate frequency (IF) level detection scheme to a low-power complex fifth-order continuous-time(CT) bandpass L:tl modulator in order to digitalize the receiver. By the continuous-time bandpass architecture, the proposed $\Sigma\Delta$ modulator requires no additional anti-aliasing filter in front of the modulator. Using the IF detector, the achieved dynamic range(DR) of the over-all system is 95 dB at a sampling rate of 64 MHz. This modulator has a bandwidth of 2 MHz centered at 2 MHz. The power consumption of this receiver is 9.0 mW with a 1.8 V power supply.

• Journal of Positioning, Navigation, and Timing
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• 제8권1호
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• pp.1-12
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• 2019

In this paper, we implement a navigation software of a Global Navigation Satellite System (GNSS) receiver based on a commercial purpose GNSS software receiver platform and verify its performance by performing experimental tests for various GNSS signals available in Korea region. The SX3, employed in this paper, is composed of an application program and a Radio Frequency (RF) frontend, and can capture and process multi-constellation and multi-frequency GNSS signals. All the signal processing procedure of SX3 is accessible by the receiver software designer. In particular for an easy research and development, the Application Programing Interface (API) of the SX3 has a flexible architecture to upgrade or change the existing software program, equipped with a real-time monitoring function to monitor all the API executions. Users can easily apply and experiment with the developed algorithms using a form of Dynamic Link Library (DLL) files. Thus, by utilizing this flexible architecture, the cost and effort to develop a GNSS receiver can be greatly reduced.

• 한국정보처리학회논문지
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• 제6권2호
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• pp.396-407
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• 1999

A Multicast transfer is a critical delivery method to provide a transport service to multipeer applications, the various problems on the multicast transfer environments have been occurred from the results of current research. One of these problems is the multicast transport service issue to guarantee reliability and scalability. First, this paper presents the related research of the reliable multicast transport methods, and then proposes a new transfer architecture using the Agent Sender and Receiver Concept(ASRC) to solve a reliable multicast transfer issue. we also propose a method to apply the proposed architecture(ASRC) to the well-known sender-initiated and receiver-initiated transport protocol. In order 새 validate the proposed ASRC architecture, t도 applied sender and receiver system si compared and analyzed over the processing requirement and maximum throughput.

• Journal of Communications and Networks
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• 제4권4호
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• pp.344-350
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• 2002

This work summarizes the current state of the art in software radio for 4G systems. Specifically, this work demonstrates that classic radio structures, e.g., heterodyne reception, homodyne reception, and their improved implementations, are inadequate selections for multi-mode reception. This opens the door to software defined radio, a novel reception architecture which promises ease in multi-band, multi-protocol design. The work presents the many advantages of such an architecture, including flexibility, reduced cost via component reduction, and improved reliability via, e.g., the elimination of environmental instability. The work also explains the limitations that currently curtail the widespread use of SDR, including issues surrounding A/D converters, management of software and power, and clock generation. This provides direction for future research to enable the broad applicability of SDR in 4G cellular and beyond.

• 전기전자학회논문지
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• 제17권2호
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• pp.176-181
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• 2013

This paper presents a CMOS impulse radio ultra-wideband (IR-UWB) receiver implemented using IBM 0.13um CMOS technology for inner/inter-chip wireless interconnection. The IR-UWB receiver is based on the non-coherent architecture which removes the complexity of RF architecture (such as DLL or PLL) and reduces power consumption. The receiver consists of three blocks: a low noise amplifier (LNA) with active balun, a correlator, and a comparator. Simulation results show the die area of the IR-UWB receiver of 0.2mm2, a power gain (S21) of 12.5dB, a noise figure (NF) of 3.05dB, an input return loss (S11) of less than -16.5dB, a conversion gain of 18dB, a NFDSB of 22. The receiver exhibits a third order intercept point (IIP3) of -1.3dBm and consumes 22.9mW of power on the 1.4V power supply.