• Journal of Korea Society of Industrial Information Systems
• /
• v.18 no.2
• /
• pp.35-40
• /
• 2013

In this paper, we propose a new image rejection receiver architecture using simultaneously the high-side and low-side injected LO signals. The proposed architecture has a lower noise figure (NF) performance and a higher linearity characteristic than the previous receiver architecture using a single LO signal. Also, the proposed receiver shows a higher IRR performance about 6dB than that of the previous Weaver image rejection architecture even though the same gain and phase errors between I-path and Q-path exist. To verify these characteristics, we derive an IRR formular of the proposed architecture as a function of mismatch parameters. And we demonstrate its formular's usefulness through the system simulation. Therefore, the proposed architecture will be widely used to implement the image rejection receiver due to its higher IRR performance.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.47 no.8
• /
• pp.24-31
• /
• 2010

A receiver architecture with low complexity for chirp spread spectrum (CSS) of IEEE 802.15.4a is proposed. To demodulate the received signal at the highest signal to noise power ratio, matched filter is generally adopted for the receiver of wireless communication systems. It is, however, not resonable to adjust the matched filter to the receiver of CSS whose objectives are low complexity, low cost and low power consumption since complexity of the matched filter is high. In this paper, we propose a new receiver architecture using differential multiplication and accumulator not matched filter for demodulation. Also, bi-orthogonal decoder implemented by only adder/subtractor is proposed. The hardware resources for implementation are reduced in the proposed receiver architecture, although bit error rate performance is low compared with the receiver architecture based on the matched filter.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.8 no.4
• /
• pp.277-282
• /
• 2008

A fully integrated inductorless CMOS impulse radio ultra-wideband (IR-UWB) receiver is implemented using $0.18\;{\mu}m$ CMOS technology for 3-5 GHz application. The UWB receiver adopts the non-coherent architecture, which removes the complexity of RF architecture and reduces power consumption. The receiver consists of inductorless differential three stage LNA, envelope detector, variable gain amplifier (VGA), and comparator. The measured sensitivity is -70 dBm in the condition of 5 Mbps and BER of $10^{-3}$. The receiver chip size is only $1.8\;mm\;{\times}\;0.9\;mm$. The consumed current is 15 mA with 1.8 V supply.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2002.11a
• /
• pp.9-14
• /
• 2002

Direct-conversion receiver(DCR) architecture has superior advantages in size, cost, and power over superheterodyne receiver architectures. However, the use of direct-conversion receiver architecture has been limited due to the direct-current offset noise. The ac coupling, which is used to overcome the direct-current offset noise, causes an inter-symbol interference(ISI), whose effects can be effectively mitigated using an equalizer. In this paper, the performance of a direct-conversion receiver with ac coupling in the presence of direct-current offset is analyzed via computer simulation. The simulation result shows that by using decision feedback equalizer with LMS(Least Mean Square) algorithm, signal-to-noise ratio loss of the direct-conversion receiver compared to the idea receiver can be reduced to less than 1㏈ for corner frequencies as large as 10% of the symbol rate.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.1
• /
• pp.6-14
• /
• 2011

This paper presents a high-speed QR decomposition architecture for the multi-input-multi-output (MIMO) receiver based on Givens rotation. Under fast-varying channel, since the inverse matrix calculation has to be performed frequently in MIMO receiver, a high performance and low latency QR decomposition module is highly required. The proposed QR decomposition architecture is composed of Sign-Select Lookahead (SSL) coordinate rotation digital computer (CORDIC). In the SSL-CORDIC, the sign bits, which are computed ahead to select which direction to rotate, are used to select one of the last iteration results, therefore, the data dependencies on the previous iterations are efficiently removed. Our proposed QR decomposition module is implemented using TSMC 0.25 ${\mu}M$ CMOS process. Experimental results show that the proposed QR architecture achieves 34.83% speed-up over the Compact CORDIC based architecture for the 4 ${\times}$ 4 matrix decomposition.

• Journal of electromagnetic engineering and science
• /
• v.8 no.2
• /
• pp.76-83
• /
• 2008

A low power(9 mW) highly-digitized 2.4 GHz receiver for sensor network applications(IEEE 802.15.4 LR-WPAN) is realized by a $0.18{\mu}m$ CMOS process. We adopted a novel receiver architecture adding an intermediate frequency (IF) level detection scheme to a low-power complex fifth-order continuous-time(CT) bandpass L:tl modulator in order to digitalize the receiver. By the continuous-time bandpass architecture, the proposed $\Sigma\Delta$ modulator requires no additional anti-aliasing filter in front of the modulator. Using the IF detector, the achieved dynamic range(DR) of the over-all system is 95 dB at a sampling rate of 64 MHz. This modulator has a bandwidth of 2 MHz centered at 2 MHz. The power consumption of this receiver is 9.0 mW with a 1.8 V power supply.

• Journal of Positioning, Navigation, and Timing
• /
• v.8 no.1
• /
• pp.1-12
• /
• 2019

In this paper, we implement a navigation software of a Global Navigation Satellite System (GNSS) receiver based on a commercial purpose GNSS software receiver platform and verify its performance by performing experimental tests for various GNSS signals available in Korea region. The SX3, employed in this paper, is composed of an application program and a Radio Frequency (RF) frontend, and can capture and process multi-constellation and multi-frequency GNSS signals. All the signal processing procedure of SX3 is accessible by the receiver software designer. In particular for an easy research and development, the Application Programing Interface (API) of the SX3 has a flexible architecture to upgrade or change the existing software program, equipped with a real-time monitoring function to monitor all the API executions. Users can easily apply and experiment with the developed algorithms using a form of Dynamic Link Library (DLL) files. Thus, by utilizing this flexible architecture, the cost and effort to develop a GNSS receiver can be greatly reduced.

• The Transactions of the Korea Information Processing Society
• /
• v.6 no.2
• /
• pp.396-407
• /
• 1999

A Multicast transfer is a critical delivery method to provide a transport service to multipeer applications, the various problems on the multicast transfer environments have been occurred from the results of current research. One of these problems is the multicast transport service issue to guarantee reliability and scalability. First, this paper presents the related research of the reliable multicast transport methods, and then proposes a new transfer architecture using the Agent Sender and Receiver Concept(ASRC) to solve a reliable multicast transfer issue. we also propose a method to apply the proposed architecture(ASRC) to the well-known sender-initiated and receiver-initiated transport protocol. In order 새 validate the proposed ASRC architecture, t도 applied sender and receiver system si compared and analyzed over the processing requirement and maximum throughput.

• Journal of Communications and Networks
• /
• v.4 no.4
• /
• pp.344-350
• /
• 2002

This work summarizes the current state of the art in software radio for 4G systems. Specifically, this work demonstrates that classic radio structures, e.g., heterodyne reception, homodyne reception, and their improved implementations, are inadequate selections for multi-mode reception. This opens the door to software defined radio, a novel reception architecture which promises ease in multi-band, multi-protocol design. The work presents the many advantages of such an architecture, including flexibility, reduced cost via component reduction, and improved reliability via, e.g., the elimination of environmental instability. The work also explains the limitations that currently curtail the widespread use of SDR, including issues surrounding A/D converters, management of software and power, and clock generation. This provides direction for future research to enable the broad applicability of SDR in 4G cellular and beyond.

• Journal of IKEEE
• /
• v.17 no.2
• /
• pp.176-181
• /
• 2013

This paper presents a CMOS impulse radio ultra-wideband (IR-UWB) receiver implemented using IBM 0.13um CMOS technology for inner/inter-chip wireless interconnection. The IR-UWB receiver is based on the non-coherent architecture which removes the complexity of RF architecture (such as DLL or PLL) and reduces power consumption. The receiver consists of three blocks: a low noise amplifier (LNA) with active balun, a correlator, and a comparator. Simulation results show the die area of the IR-UWB receiver of 0.2mm2, a power gain (S21) of 12.5dB, a noise figure (NF) of 3.05dB, an input return loss (S11) of less than -16.5dB, a conversion gain of 18dB, a NFDSB of 22. The receiver exhibits a third order intercept point (IIP3) of -1.3dBm and consumes 22.9mW of power on the 1.4V power supply.