• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.369-378
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• 2003

This paper presents design and VLSI implementations of a reassembly processor for ATM/AAL. The assembly processor is responsible for processing ATM cells from the receive physical interface. It controls the transfer of the AAL payload to host memory and performs all necessary SAR and CPCS checks. We propose the improved structure of cell identification algorithm and smart scatter method for host memory management. The proposed cell identification algorithm quickly locates the appropriate reassembly VC table based on the received VPI./VCI channel value in the ATM header. The cell identification algorithm also allow complete freedom in assignment of VCI/VPI values. The reassembly processor uses a smart scatter method to write cell payload data to host memory. It maintains the scatter operation and controls the incoming DMA block during scatter DMA to host memory. The proposed reassembly processor can perform reassembly checks on AAL. OAM cell. For an AAL5 connection, only CPCS checks, including the CRC32, are performed. In this paper, we proposed a practical reassembly architecture. The design of reassembly processor has become feasible using 0.6${\mu}{\textrm}{m}$ CMOS gate array technology.

• ETRI Journal
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• v.17 no.1
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• pp.23-36
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• 1995

We present a performance evaluation model of cell reassembly mechanism in an ATM switching system. An ATM switching system may be designed so that communications between processors of its control part can be performed via its switching network rather than a separate inter-processor communications network. In such a system, there should be interface to convert inter-processor communication traffic from message format to cell format and vice versa, that is, mechanisms to perform the segmentation and reassembly sublayer. In this paper, we employ a continuous-time Markov chain for the performance evaluation model of cell reassembly mechanism with individual buffering, judicially defining the states of the mechanism. Performance measures such as message loss probability and average reassembly delay are obtained in closed forms. Some numerical illustrations are given for the performance analysis and dimensioning of the cell reassembly mechanism.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.3
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• pp.213-218
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• 2008

This paper describes hardware-based high speed multimedia data reassembly processor for remote multimedia Set-Top-Box(MSTB) of interactive satellite multimedia communication system. The conventional multimedia data reassembly scheme is based on software processing of MSTB. As increasing of transmission rate for multimedia data services, the CPU load of remote MSTB is increased and reassembly performance of MSTB is limited. To provide high speed multimedia data service to end user, we proposed hardware based high speed multimedia data reassembly processor. It is implemented by using an FPGA, a PCI interface chip, and RAMs. And it is integrated in MSTB and tested. It has been confirmed to meet required all functions and processing rate up to 116Mbps.

• Journal of the Korean Operations Research and Management Science Society
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• v.22 no.2
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• pp.139-151
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• 1997

An ATM switching system may be designed so that communications between processors of its control part can be performed via its switching network rather than a separate inter-processor communications (IPC) network. In such a system, there should be interfaces to convent IPC traffic from message format to cell format and vice versa, that is, mechanisms to perform the SAR (Segmentation And Reassembly) sublayer functions. In this paper, we concern the cell reassembly mechanism among them, mainly focussed on buffer management schemes. We consider a few alternatives to implement cell reassembly function block, namely, separated buffering, reserved buffering and shared buffering in this paper. In case of separated and reserved buffering, we employ a continuous time Markov chain for the performance evaluation of cell reassembly mechanism, judicially defining the states of the mechanism. Performance measures such as measage loss probability, mean number of message queued in buffer and average reassembly delay are obtianed in closed forms. In case of shared buffering, we compare the alternatives for implementing cell reassembly function block using simulation because it is almost impossible to analyze the mechanism of shared buffering by analytical modeling. Some illustrations are given for the performance analysis of the alternatives to implement cell reassembly function block.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.10b
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• pp.1379-1382
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• 2001

본 논문에서는 ATM 망에서의 통합 네트워크 구현을 위한 IP data packet를 처리하기 위한 AAL type5 프로토콜 프로세서를 설계 및 구현하였다. AAL 계층의 중요 기능들은 ITU-T Recommendation 1.363과 1.363.5 에 근거하여 설계하였다. AAL 계층의 주요한 역할은 데이터의 Segmentation 및 셀의 Reassembly를 하는 것으로, Segmentation 과정에서는 상위 계층의 연속적인 데이터를 Segmentation하여 53-byte 크기의 ATM 셀을 구성하는 기능이다. Reassembly 과정에서는 들어오는 셀들을 연속적인 데이터로 만들어 AAL 계층 보다 상위 계층으로 전달하는 것이다. 이 과정에서 셀의 Header 를 확인한 후 crc-32를 통한 오류 검정을 거치게 되며, 데이터에 오류가 있을 경우에는 해당 셀을 버리고 오류가 없을 시에만 상위 계층으로 전달한다. 본 논문에서 구현한 AAL Type 5 프로세서는 향후 모든 Type의 data를 수용하는 칩 개발에 유용할 것으로 사료된다. 본 논문에서 원할한 테스트를 위해 데이터의 loop back 신호 DLB를 사용했다 VHDL 해석기로는 Synopsys 사의 VHDL Analyzer를 사용하였고, Design Compiler로 회로를 합성하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.04b
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• pp.689-692
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• 2001

본 논문에서는 ATM 망에서 CBR(Constant Bit Rate) 트래 픽 전송을 위한 AAL(ATM Adaptation Layer) type 1 프로세서를 설계 및 구현하였다. AAL 계층의 중요 기능들은 ITU-T Recommendations I.362 와 I.363 에 근거하여 설계하였다. AAL 계층의 주요한 역할은 데이터의 Segmentation 및 셀의 Reassembly 를 하는 것으로, Segmentation 과정에서는 상위 계층의 연속적인 데이터를 Segmentation 하여 53-byte 크기의 ATM 셀을 구성하는 기능이다. Reassembly 과정에서는 들어오는 셀들을 연속적인 데이터로 만들어 AAL 계층 보다 상위 계층으로 전달하는 것이다. 이 과정에서 셀의 Header 를 확인한 후 오류 검정을 거치게 되며, 데이터에 오류가 있을 경우에는 해당 셀을 버리고 오류가 없을 시에만 상위 계층으로 전달한다. 본 논문에서 구현한 Simple AAL type1 프로세서는 향후 모든 type 의 AAL 을 수용하는 칩 개발에 유용할 것으로 사료된다.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.289-440
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• 1998

This paper describes an interconnection network structure which transports information among processors through a high speed ATM switch. To efficiently use the high speed ATM switch for the message-based multiprocessor, we implemented the cell router that performs multiplexing and demultiplexing of cells from/to processors. In this system, we use the expanded internal cell format including 3bytes for switch routing information. This interconnection network has 3 stage routing strategies: ATM switch routing using switch routing information, cell router routing using a virtual path identifier (VPI) and cell reassembly routing using a virtual channel indentifier (VCI). The interconnection network consists of the NxN folded switch and N cell routers with the M processor interface. Therefore, the maximum number of NxM processors can be interconnected for message communication. This interconnection network using the ATM switch makes a significant improvement in terms of message passing latency and scalability. Additionally, we evaluated the transmission overhead in this interconnection network using ATM switch.