• 제목/요약/키워드: Real-time decoding

검색결과 162건 처리시간 0.023초

Efficient Hardware Implementation of Real-time Rectification using Adaptively Compressed LUT

  • Kim, Jong-hak;Kim, Jae-gon;Oh, Jung-kyun;Kang, Seong-muk;Cho, Jun-Dong
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제16권1호
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    • pp.44-57
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    • 2016
  • Rectification is used as a preprocessing to reduce the computation complexity of disparity estimation. However, rectification also requires a complex computation. To minimize the computing complexity, rectification using a lookup-table (R-LUT) has been introduced. However, since, the R-LUT consumes large amount of memory, rectification with compressed LUT (R-CLUT) has been introduced. However, the more we reduce the memory consumption, the more we need decoding overhead. Therefore, we need to attain an acceptable trade-off between the size of LUT and decoding overhead. In this paper, we present such a trade-off by adaptively combining simple coding methods, such as differential coding, modified run-length coding (MRLE), and Huffman coding. Differential coding is applied to transform coordinate data into a differential form in order to further improve the coding efficiency along with Huffman coding for better stability and MRLE for better performance. Our experimental results verified that our coding scheme yields high performance with maintaining robustness. Our method showed about ranging from 1 % to 16 % lower average inverse of compression ratio than the existing methods. Moreover, we maintained low latency with tolerable hardware overhead for real-time implementation.

Implementation of efficient multi-view system through function distribution in digital multi-channel broadcasting service

  • Kwon, Myung-Kyu
    • 한국컴퓨터정보학회논문지
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    • 제22권6호
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    • pp.17-24
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    • 2017
  • In recent digital broadcasting, up to 250 channels are multiplexed and transmitted. The channel transmission is made in the form of MPEG-2 Transport Stream (TS) and transmits one channel (Video, Audio). In order to check if many broadcast channels are transmitted normally, in multi-channel multi-view system, ability of real-time monitoring is required. In order to monitor efficient multi-channel, a distributed system in which functions and load are distributed should be implemented. In the past, we used an inefficient system that gave all of the functionality to a piece of hardware, which limited the channel acceptance and required a lot of resources. In this paper, we implemented a distributed multi-view system which can reduce resources and monitor them economically through efficient function and load balancing. It is able to implement efficient system by taking charge of decoding, resizing and encoding function in specific server and viewer function in separate server. Through this system, the system was stabilized, the investment cost was reduced by 19.7%, and the wall monitor area was reduced by 52.6%. Experimental results show that efficient real-time channel monitoring for multi-channel digital broadcasting is possible.

Design and Architecture of Low-Latency High-Speed Turbo Decoders

  • Jung, Ji-Won;Lee, In-Ki;Choi, Duk-Gun;Jeong, Jin-Hee;Kim, Ki-Man;Choi, Eun-A;Oh, Deock-Gil
    • ETRI Journal
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    • 제27권5호
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    • pp.525-532
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    • 2005
  • In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix-4, center to top, parallel decoding, and early-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field-programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.

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Extension of Real Time Execution in MMS Implementation

  • Kim, Dong-Sung;Lee, Jae-Min;Kim, Hyung-Suk;Kwon, Wook-Hyun
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1999년도 제14차 학술회의논문집
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    • pp.69-72
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    • 1999
  • In this paper, the implementation method for the extending real-time execution in MMS Implementation is proposed. For this, the method of MMS over ATM(Asynchronous Transfer Mode) and IEEE 802.12 network is analyzed. By the analysis of service response time, making the ASIC of encoding and decoding parts are proposed for one of the real time extension in MMS. The main goals of this paper to analyze and propose suitable methods to meet the real time requirements in MMS applied system.

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A New Mobile Watermarking Scheme Based on Display-capture

  • Bae, Jong-Wook;Jung, Sung-Hwan
    • 한국멀티미디어학회논문지
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    • 제12권6호
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    • pp.815-823
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    • 2009
  • Most of existing watermarking schemes insert and extract a watermark, focusing on the visual conservation of an original image. However, existing watermarking schemes could be difficult for a watermark detection in case of various distortion caused by display-capture devices. Therefore, we propose a new display-capture based mobile watermarking scheme. The proposed watermarking scheme is a new concept for embedding a watermark, which uses the generated image instead of a given original image. For effective watermark decoding, we also present a method for detecting the background image whose error bit can not be corrected because of various heavy distortion and for avoiding it from the decoding process. For this scheme, we adopt distortion coefficients of camera calibration when we separate a background image from a captured image. For finding available correction bits of ECC through the decoding process, we capture 30,000 images and then calculate the separation ratio of a background image and the average error bits per an image. As experimental result, the separation ratio of a background image is about 96.5% in 30,000 captured image. And the false alarm ratio shows about $5.18{\times}10^{-4}$ in the separated background image. And also we can confirm the availability of real-time processing because the mean execution time is about 82ms per an image for capturing and decoding.

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Complexity Analysis of Internet Video Coding (IVC) Decoding

  • Park, Sang-hyo;Dong, Tianyu;Jang, Euee S.
    • Journal of Multimedia Information System
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    • 제4권4호
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    • pp.179-188
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    • 2017
  • The Internet Video Coding (IVC) standard is due to be published by Moving Picture Experts Group (MPEG) for various Internet applications such as internet broadcast streaming. IVC aims at three things fundamentally: 1) forming IVC patents under a free of charge license, 2) reaching comparable compression performance to AVC/H.264 constrained Baseline Profile (cBP), and 3) maintaining computational complexity for feasible implementation of real-time encoding and decoding. MPEG experts have worked diligently on the intellectual property rights issues for IVC, and they reported that IVC already achieved the second goal (compression performance) and even showed comparable performance to even AVC/H.264 High Profile (HP). For the complexity issue, however, there has not been thorough analysis on IVC decoder. In this paper, we analyze the IVC decoder in view of the time complexity by evaluating running time. Through the experimental results, IVC is 3.6 times and 3.1 times more complex than AVC/H.264 cBP under constrained set (CS) 1 and CS2, respectively. Compared to AVC/H.264 HP, IVC is 2.8 times and 2.9 times slower in decoding time under CS1 and CS2, respectively. The most critical tool to be improved for lightweight IVC decoder is motion compensation process containing a resolution-adaptive interpolation filtering process.

터보코드에 적용을 위한 세미 랜덤 인터리버 알고리즘의 제안 (The Presentation of Semi-Random Interleaver Algorithm for Turbo Code)

  • 홍성원;박진수
    • 한국정보처리학회논문지
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    • 제7권2호
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    • pp.536-541
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    • 2000
  • 터보코드는 인터리버의 크기가 클수록 반복 복호횟수가 많을수록 복호 성능은 우수하지만 시스템이 복잡해져 한 개의 정보비트를 복호할 때 많은 시간지연을 발생시켜 실시간 통신에는 부적합하다는 단점이 있다. 따라서 본 논문에서는 터보코드 부$\cdot$복호기에 사용되는 인터리버의 크기를 감소시켜 한 개의 정보비트를 복호할 때 소요되는 시간지연을 줄이는 새로운 세미 랜덤(Semi-Random) 인터리버 알고리즘을 제안하였다. 세미 랜덤 인터리버 알고리즘은 입력 데이터 길이의 1/2 크기만큼 인터리버를 구성하고, 인터리버 내에 쓸때는 블록 인터리버처럼 행으로 쓰고, 읽을 때는 랜덤하게 읽음과 동시에 다음 데이터가 그 주소 번지에 위치하게 된다. 따라서 기존의 블록, 대각, 랜덤 인터리버와 알고리즘의 복잡도를 비교할 시 그 복잡도를 1/2로 감소시킬 수 있게 된다.

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H.264/AVC 디코더의 움직임 보상을 위한 메모리 접근 감소 기법 (Memory Access Reduction Scheme for H.264/AVC Decoder Motion Compensation)

  • 박경오;홍유표
    • 한국통신학회논문지
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    • 제34권4C호
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    • pp.349-354
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    • 2009
  • H.264/AVC 디코더의 하드웨어 구현 시 실시간 동작을 위한 가장 큰 장애 요소 중 하나인 외부 메모리 엑세스량을 크게 줄인 움직임 보상 기법을 제안한다. H.264/AVC 디코더의 움직임 보상용 참조 영상은 큰 용량 때문에 대게 외부 메모리에 보관되며, 참조 영역은 수시로 디코더 코어 내부로 읽혀지게 되는데, 단순히 참조 영역 단위별 순차적 메모리 접근을 할 경우 그 데이터 엑세스 량은 디코더의 실시간 동작이 불가능할 정도로 막대할 수가 있다. 본 논문에서는 참조 영역을 매크로블럭 단위로 분석하여 가급적 적은 메모리 엑세스로 필요한 참조 영역을 읽어 들이는 방식을 제안하고 있으며, 실험 결과 제안된 움직임 보상 기법은 단순한 순차적 참조 블록별 데이터 접근 방식 대비 외부 메모리 사용 대역폭을 약 30% 감소시킴을 확인할 수 있었다.

A 18-Mbp/s, 8-State, High-Speed Turbo Decoder

  • Jung Ji-Won;Kim Min-Hyuk;Jeong Jin-Hee
    • Journal of electromagnetic engineering and science
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    • 제6권3호
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    • pp.147-154
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    • 2006
  • In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de) interleaving and iterative decoding in a conventional maximum a posteriori(MAP) turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is come from the combination of the radix-4, dual-path processing, parallel decoding, and rearly-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit-error rate(BER) performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. Fixed on the parameters of N=212, iteration=3, 8-states, 3 iterations, and QPSK modulation scheme, we designed the adaptive high-speed turbo decoder using the Xilinx chip (VIRTEX2P (XC2VP30-5FG676)) with the speed of 17.78 Mb/s. From the results, we confirmed that the decoding speed of the proposed decoder is faster than conventional algorithms by 8 times.

멀티쓰레드와 SIMD 명령어를 이용한 실시간 H.264/AVC High 4:4:4 Predictive 디코더의 구현 (Real-time H.264/AVC High 4:4:4 Predictive Decoder Using Multi-Thread and SIMD Instructions)

  • 김용환;김재우;최병호;이석필;백준기
    • 한국정보통신설비학회:학술대회논문집
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    • 한국정보통신설비학회 2007년도 학술대회
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    • pp.350-353
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    • 2007
  • This paper presents an real-time implementation of H.264/AVC High 4:4:4 Predictive profile decoder using general-purpose processors by exploiting multi-threading technique and Single Instruction Multiple Data (SIMD) instructions without any quality degradation. We analyze differences between the existing High profile and High 4:4:4 Predictive profile decoder, and show various optimization techniques to decode high fidelity and high definition (HD) video in real-time. Simulation results show that the proposed decoder can play high fidelity HD video at average 40 frames per seconds (fps) for the IBBrBP bistream and about 50 fps for the Intra-only bitstream.

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