• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.61-66
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• 1992

In this paper, a method for implementing software for the control system with dual structure in processor module is proposed and implemented to enhance its reliability. In this implementation the multi-tasking function which is provided by a real-time operating system is applied. The overall softwre is divided into five tasks and is performed in each of the dual processor module, independently. By this, the processor module with dual structure can achieve a control objective and fault diagnostics effectively. An experimental result shows that the backup processor module can be substituted for the primary processor module immediately when it happens to fail, because data relating the failure information are exchanged continuously done via shared memories.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.6
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• pp.1019-1024
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• 2006

A system design and realization for real time DVR system with robust video watermarking algorithm for contents security is presented in this paper. The robust video watermarking is used the intraframe space region and interframe insertion simultaneously, and to be processed at real time on image data and algorithm is used the 64bits special purpose quad DSP processor with assembly and soft pipeline codes. The experimental result shows that the processing time takes about 2.5ms in the D1 image per frame for 60% moving image.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.963-971
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• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.313-316
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• 2002

This paper presents the design and implementation of a crypto processor, a special-purpose microprocessor optimized for the execution of cryptography algorithms. This crypto processor can be used fur various security applications such as storage devices, embedded systems, network routers, etc. The crypto processor consists of a 32-bit RISC processor block and a coprocessor block dedicated to the SEED and triple-DES (data encryption standard) symmetric key crypto (cryptography) algorithms. The crypto processor has been designed and fabricated as a single VLSI chip using 0.5 $\mu\textrm{m}$ CMOS technology. To test and demonstrate the capabilities of this chip, a custom board providing real-time data security for a data storage device has been developed. Testing results show that the crypto processor operates correctly at a working frequency of 30MHz and a bandwidth o1240Mbps.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.10
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• pp.1081-1087
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• 2008

This paper describes limitations and solutions of the existing processor-monitoring concept for a military supersonics aircraft Flight Control Computer (FLCC) equipped with modern architecture processor to perform the system integration test. Safecritical FLCC integration test, which requires automatic test for thousands of test cases and real-time input/output test condition generation, depends on the processor-monitoring device called Processor Interface (PI). The PI, which relies upon on the FLCC processor's external address and data-bus data, has some limitations due to multi-fetching capability of the modern sophisticated military processors, like C6000's VLIW (Very-Long Instruction Word) architecture and PowerPC's Superscalar architecture. Several techniques for limitations were developed and proper monitoring approach was presented for modem processor-adopted FLCC system integration test.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.6
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• pp.79-85
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• 2019

Recently, small radar require the development of small millimeter wave radar with high distance resolution to disable the target's system with a single strike. Small millimeter wave radar with high distance resolution need to process large amounts of data in real time to acquire and track target. In this paper, we summarized the real-time data preprocessing method to process the large amount of data required for small millimeter wave radar. In addition, the digital IF(Intermediate Frequency) receiver, Window processing, and, DFT(Discrete Fourier Transform) functions presented by real-time data preprocessing are implemented using FPGA(Field Programmable Gate Array). Finally the implemented real-time data preprocessing module was applied to the signal processor for small millimeter wave radar and verified by performance test related to the real-time preprocessing function.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.6
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• pp.1069-1076
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• 2019

With the development of information and communication technology, the military's battle environment is changing greatly to network centric warfare in where weapon system is connected in a network and carries out mission by exchanging the real-time data. The core of the network centric warfare is Tactical Data Link(TDL) system, and subscribers of TDL exchange tactical information in real time through wireline, wireless and satellite network to share the battlefield situation. The amount of data sent and received through TDL inevitably increase as military's weapon systems equipped with TDL systems increase over time and the performance of communications equipment improves. This study proposes ways to improve the transmission speed and processing capacity of the TDL system by improving the Data Link Processor.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.373-376
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• 2001

This paper has been studied a real-time video frame data processing control that used the linear systolic array for motion estimation. The proposed data control processing provides to the input data into the multiple processor array unit(MPAU) from search area and reference block data. The proposed data control architecture has based on two slice band for input data processing. And it has no required external control logic blocks for input data as like reference block or search area data.

• The KIPS Transactions:PartA
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• v.18A no.1
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• pp.1-10
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• 2011

Physical modeling has been widely used for sound synthesis since it synthesizes high quality sound which is similar to real-sound for musical instruments. However, physical modeling requires a lot of parameters to synthesize a large number of sounds simultaneously for the musical instrument, preventing its real-time processing. To solve this problem, this paper proposes a single instruction, multiple data (SIMD) based multi-core processor that supports real-time processing of sound synthesis of gayageum which is a representative Korean traditional musical instrument. The proposed SIMD-base multi-core processor consists of 12 processing elements (PE) to control 12 strings of gayageum in which each PE supports modeling of the corresponding string. The proposed SIMD-based multi-core processor can generate synthesized sounds of 12 strings simultaneously after receiving excitation signals and parameters of each string as an input. Experimental results using a sampling reate 44.1 kHz and 16 bits quantization show that synthesis sound using the proposed multi-core processor was very similar to the original sound. In addition, the proposed multi-core processor outperforms commercial processors(TI's TMS320C6416, ARM926EJ-S, ARM1020E) in terms of execution time ($5.6{\sim}11.4{\times}$ better) and energy efficiency (about $553{\sim}1,424{\times}$ better).