• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 춘계학술대회 논문집
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• pp.40-40
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• 2010

CdSe nanocrystals (NCs) have been decorated on singlewalled carbon nanotubes (SWCNTs) by combining a method of chemically modified substrate along with gate-bias control. CdSe/ZnS core/shell quantum dots were negatively charged by adding mercaptoacetic acid (MAA). The silicon oxide substrate was decorated by octadecyltrichlorosilane (OTS) and converted to hydrophobic surface. The negatively charged CdSe NCs were adsorbed on the SWCNT surface by applying the negative gate bias. The selective adsorption of CdSe quantum dots on SWCNTs was confirmed by confocal laser scanning microscope. The measured photocurrent clearly demonstrates that CdSe NCs decorated SWCNT can be used for photodetector and solar cell that are operable over a wide range of wavelengths.

• 전자공학회논문지
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• 제49권12호
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• pp.173-178
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• 2012

RF 직접 추출 방법을 통해 얻은 정확한 MOSFET 기판 파라미터를 이용하여 기판저항만을 가진 BSIM4 모델은 스케일링 부정확성 때문에 넓은 영역의 게이트 길이에 적용하기에는 물리적으로 맞지 않다는 것이 증명됐다. BSIM4의 비물리적인 문제점을 제거하기 위해서 추가적인 유전체 기판 캐패시터를 가진 수정된 BSIM4 모델이 사용되었고, 이 모델의 물리적 타당성은 우수한 게이트 길이 scalability를 관찰함으로써 증명되었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.217-220
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• 2002

In this paper, we have investigated electronical chara-cteristics of power LDMOSFETS having different ex-tended gate lengths(1.B${\mu}{\textrm}{m}$, 2.4${\mu}{\textrm}{m}$, 3.O${\mu}{\textrm}{m}$) in the temperature range of 300k-500K. The results of this study indicate that on-resistance, breakdown voltage increase with temperature. and drain current, threshold voltage, transconductance decrease with temperature. Particular the facts, we observed that Le is the more increase, on-resistance is the more decrease. because every conditions are fixed normal states, only change the Le. As a result, Ron/BV, known for a figure of merit of power device, increase with temperature.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.249-252
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• 2002

we have studied the characteristics of PHEMT's with gate recess etching method. The DC characterization of PHTMT fabricated with the wide single recess methods is a maximum drain current density of 319.4 ㎃/mm and a peak transconductance of 336.7 ㎳/mm. The RF measurements were obtained in the frequency range of 1~50GHz. At 50GHz, 3.69dB of 521 gain were obtained and a current gain cut-off frequency(f$_{T}$) of 113 CH and a maximum frequency of oscillation(f$_{max}$) of 172 Ghz were achieved from this device. On the other hand, a maximum drain current of 367 mA/mm, a peak transconduclancc of 504.6 mS/mm, S$_{21}$ gain of 2.94 dB, a current gain cut-off frequency(f$_{T}$) of 101 CH and a maximum frequency of oscillation(f$_{max}$) of 113 fa were achieved from the PHEMT's fabricated by the .narrow single recess methods.methods.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.193-196
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• 2002

This paper presents the improvement of the boron penetration and the reverse short channel effect (RSCE) in the 130nm W/WNx/Poly-Si dual gate PMOSFET for a high performance embedded DRAM. In order to suppress the boron penetration, we studied a range in the process heat budget. It has shown that the process heat budget reduction results in suppression of the boron penetration. To suppress the RSCE, we experimented with the halo (large tilt implantation of the same type of impurities as those in the device well) implant condition near the source/drain. It has shown that the low angle of the halo implant results in the suppression of the RSCE. The experiment was supported from two-dimensional(2-D) simulation, TSUPREM4 and MEDICI.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권6호
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• pp.569-575
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• 2013

An improved non-quasi-static gate-source impedance model including a parallel RC block for short-channel MOSFETs is developed to simulate RF MOSFET input characteristics accurately in the wide range of high frequency. The non-quasi-static model parameters are accurately determined using the physical input equivalent circuit. This improved model results in much better agreements between the measured and modelled input impedance than a simple one with a non-quasi-static resistance up to 40GHz, verifying its accuracy.

• 전자공학회논문지D
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• 제34D권12호
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• pp.54-61
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• 1997

An accurate extraction technique is developed to determine full euqivalent circuit parameters of Si MOSFETs using 1 set of measured S-parametes without complicated optimization process. This technique is based on the use of anlytic Z-parameters experessions for resistances and inductances and the Y-parameter ones for ntrinsic parameters. This accuracy is proved over the wide range of gate voltage by observing good agreement between measured and fitted Z-parameter equations and frequency-independent response of the extracted intrinsic parameters. Using this technique, gate voltage-dependencies of model parameters are obained in the saturation region and these results show the similar behavior to the short-channel effects expected from the device theory.

• Journal of Power Electronics
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• 제17권5호
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• pp.1372-1381
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• 2017

This paper presents a high-side switch driver IC capable of improving the current sensing accuracy and providing reverse battery protection. Power semiconductor switches used to replace relay switches are encumbered by two disadvantages: they are prone to current sensing errors and they require additional external protection circuits for reverse battery protection. The proposed IC integrates a gate driver and current sensing blocks, thus compensating for these two disadvantages with a single IC. A p-sub-based 90-V $0.13-{\mu}m$ bipolar-CMOS-DMOS (BCD) process is used for the design and fabrication of the proposed IC. The current sensing accuracy (error ${\leq}{\pm}5%$ in the range of 0.1 A-6.5 A) and the reverse battery protection features of the proposed IC were experimentally tested and verified.

• 한국컴퓨터정보학회논문지
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• 제4권4호
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• pp.57-68
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• 1999

본 논문은 게이트 레벨 디지털 시스템의 동작기술과 그 동작결과를 검증 할 수 있는 시뮬레이터를 작성하는데 목적을 두고 있다. 기술언어로부터 목적코드를 얻기 위하여 번역기를 구성한 바 이의 구현을 위하여 UNIX의 YACC를 이용하였으며 중간 목적 파일을 번역기와 시뮬레이터의 중간과정으로 삼아 응용범위를 넓힐 수 있도록 하였다. 시뮬레이션 대상으로 전가산기와 3진 계수기를 사용하였다.

• ETRI Journal
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• 제11권2호
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• pp.109-119
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• 1989

Based on the 2-dimensional charge-control simulation[4], a purely analytical model for MODFET's is proposed. In this model, proper treatment of the diffusion effect in the 2-DEG transport due to the gradual channel opening along the 2-DEG channel was made to explain the enhanced mobility and increased thershold voltage. The channel thickness and gate capacitance are experssed as functions of gate vlotage including subthreshold characteristics of the MODFET's analytically. By introducing the finite channel opening and an effective channel-length modulation, the slope of the saturation region of the I-V curves was modeled. The smooth transition of the I-V curves from linear-to-saturation region of the I-V curves was possible using the continuous Troffimenkoff-type of field-dependent mobility. Furthermore, a correction factor f was introduced to account for the finite transtition section forming between the GCA and the saturated section. This factor removes the large discrepanicies in the saturation region fo the I-V curves presicted by existing 1-dimensional models. The fitting parameters chosen in our model were found to be predictable and vary over relatively small range of values.