• 한국정밀공학회지
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• 제31권6호
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• pp.497-504
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• 2014

The digital signage display is actively researched as the next generation of large FPD. To commercialize those digital signage display, the manufacturing cost must be downed with printing method instead of conventional photolithography. Here, we demonstrate a reverse offset printed TFT electrodes for the digital signage display. For the fabricated source/drain and gate electrode, we used Ag ink, silicone blanket, Clich$\acute{e}$ and reverse offset printer. We printed uniform TFT electrode patterns with narrow line width(10 ${\mu}m$ range) and thin thickness(nm range). In the end the printing source/drain and gate electrode are successfully achieved by optimization of experimental conditions such as Clich$\acute{e}$ surface treatment, ink coating process, delay time, off/set process and curing temperature. Also, we checked that the printing align accuracy was within 5 ${\mu}m$.

• 한국기계가공학회지
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• 제13권6호
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• pp.73-81
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• 2014

In this paper, multiple gate locations and process conditions under concern are automatically optimized by considering robustness to minimize the injection pressure required to mold an automotive dashboard. Computer simulation-based experiments using orthogonal arrays(OA) and a design-range reduction algorithm are consolidated into an iterative search scheme, which is then used as a tool for the optimization process. The robustness of a design is evaluated using an OA-based simulation of process fluctuations due to noise as well as the signal-to-noise ratio. The optimal design solution for the automotive dashboard shows that the robustness of the injection pressure is significantly improved when compared to the initial design. As a result, both the die clamping force and the pressure distribution in the part cavity are also much improved in terms of their robustness.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.549-556
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• 2014

This paper proposes a highly power-efficient single-inductor multiple-outputs (SIMO) DC-DC converter with a gate charge sharing method in which gate charges of output switches are shared to improve the power efficiency and to reduce the switching power loss. The proposed converter was fabricated by using a $0.18{\mu}m$ CMOS process technology with high voltage devices of 5 V. The input voltage range of the converter is from 2.8 V to 4.2 V, which is based on a single cell lithium-ion battery, and the output voltages are 1.0 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V. Using the proposed gate charge sharing method, the maximum power efficiency is measured to be 87.2% at the total output current of 450 mA. The measured power efficiency improved by 2.1% compared with that of the SIMO DC-DC converter without the proposed gate charge sharing method.

• 대한전자공학회논문지SD
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• 제49권1호
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• pp.1-7
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• 2012

산화물 박막트랜지스터를 이용하여 액정 디스플레이 패널에 내장할 수 있는 새로운 게이트 드라이버 회로를 설계하고 제작하였다. 산화물 박막트랜지스터는 문턱전압이 음의 값을 갖는 경우가 많기 때문에 본 회로에서는 음의 게이트 전압을 인가하여 트랜지스터를 끄는 방법을 적용하였다. 또한 세 개의 풀다운 트랜지스터를 병렬로 배치하고 번갈아 사용하므로 안정적인 동작이 가능하다. 제안한 회로는 트랜지스터의 문턱전압이 -3 V ~ +6 V인 범위에서 정상적으로 동작하는 것을 시뮬레이션을 통해서 확인하였으며, 실제로 유리 기판 상에 제작하여 안정적으로 동작하는 것을 검증하였다.

• 한국전기전자재료학회논문지
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• 제13권8호
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• pp.651-657
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• 2000

The notching effect in etching of undoped amorphous silicon gate had different characteristics and mechanism comparing with reported ones. The undoped amorphous silicon was etched by using HBr gas plasma. First in the region of small line width the potential increased as a result of ions in the exposed surface of oxide and the incident ions between the small line widths were deflected more wide range therefore the depth of notching was shallow and wide. Second in the region of large line width of gate electrons were charged on the top of photoresist and the side of gate a part of ions deflected. The deflected ions were partly charged positive on the side of gate and then these partly charged ions produced potential difference. Therefore ions stored up more at independent line than at dense line and notching became deeper by Br ion bombardments.

• 대한전자공학회논문지SD
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• 제45권6호
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• pp.10-15
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• 2008

본 논문에서는 UHF RFID 응용을 위한 새로운 NMOS 게이트 교차연결 전류미러형 브리지 정류기를 제시하였다. 제시된 정류기의 직류 변환 특성은 고주파 등가회로를 이용하여 해석하였으며, 주파수 증가에 따른 게이트 누설전류를 회로적인 방법으로 줄일 수 있는 게이트 커패시턴스 감소 기법을 이론적으로 제시하였다. 구해진 결과, 제안한 정류기는 기존의 게이트 교차 연결형 정류기와 거의 같은 직류 출력전압 특성을 보이면서도, 게이트 누설전류가 1/4 이하로 감소하고, 부하저항에서의 소비전력도 30% 이상 감소하며, 부하저항의 변화에 대해 보다 안정적인 직류전압을 공급함을 알 수 있었다. 또한 제안한 정류기는 13.56MHz의 HF(for ISO 18000-3)부터 915MHz의 UHF(for ISO 18000-6) 및 2.45GHz의 마이크로파 대역 (for ISO 18000-4)까지의 전 주파수 범위에 대해 충분히 높고 잘 정류된 직류 변환 특성을 보여 특정 주파수 대역을 사용하는 다양한 RFID 시스템의 트랜스폰더 칩 구동을 위한 범용 정류기로 사용될 수 있다.

• 대한전자공학회논문지
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• 제11권2호
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• pp.40-45
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• 1974

SCR에서도 anode 전류가 미소(약수 10mA∼수100mA이내)할때에는 게이트 전fur을 조정하므로써 anode전류를 조절할수 있다. 이를 이용하여 cathode 각로에 적당치의 저항을 삽입하여 게이트 회로에 부성저항특성을 나타내게 할 수 있고 간단한 정형파 발진회로를 만들었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.361-366
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• 2013

A full-range analytic drain current model for depletion-mode long-channel surrounding-gate nanowire field-effect transistor (SGNWFET) is proposed. The model is derived from the solution of the 1-D cylindrical Poisson equation which includes dopant and mobile charges, by using the Pao-Sah gradual channel approximation and the full-depletion approximation. The proposed model captures the phenomenon of the bulk conduction mechanism in all regions of device operation (subthreshold, linear, and saturation regions). It has been shown that the continuous model is in complete agreement with the numerical simulations.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 춘계 기술심포지움 논문집
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• pp.198-202
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• 2002

$HfO_2$films were grown on Si substrate in the temperature range $250~550^{\circ}C$ using metal organic chemical vapor deposition (MOCVD) technique for a gate dielectric. Hafnium tart-butoxide and Oxygen gas were used as precursors and N2 was used as carrier gas. Impurity distribution and film structure(including interfacial layer) were studied at the deposition temperature range between 25$0^{\circ}C$ and $550^{\circ}C$. The growth rate and impurty distribution decreased with increasing temperature. The electrical properties of $HfO_2$were investigated with C-V, 1-V method and showed it has a good properties as a gate dielectric.

• 한국진공학회지
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• 제4권S1호
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• pp.108-112
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• 1995

Copper and aluminum selective deposition using (hfac)Cu(VTMS) and DMEAA precursors were performed in a warm-wall low pressure chemical vapour deposition reactor. The films of Cu and AI deposited on Corning 7059 glass and quartz with pattern of Cr seed metal. Selective deposition can be achieved at a pressure range of from 10-1 to 10 torr and substrate temperature range of 150-25$0^{\circ}C$. Selective deposition of Cu and AI by CVD is one of candidate for gate material formation fo larger area and high resolution plat panel displays.