• Journal of applied mathematics & informatics
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• v.29 no.1_2
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• pp.247-255
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• 2011

Invertible functions with a single cycle property have many cryptographic applications. The main context in which we study them in this paper is pseudo random generation and stream ciphers. In some cryptographic applications we need a generator which generates binary sequences of period long enough. A common way to increase the size of the state and extend the period of a generator is to run in parallel and combine the outputs of several generators with different period. In this paper we will characterize a secure quadratic polynomial on $\mathbb{Z}_{2^n}$, which generates a binary sequence of period long enough and without consecutive elements.

• Journal of Internet Computing and Services
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• v.8 no.5
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• pp.141-150
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• 2007

This paper proposes new Steganographic model for VoIP that has very effective method using low bit encoding. Most of Steganographic models using Low bit Encoding have two disadvantages; one is that the existence of hidden secret message can be easily detected by auditory, the other is that the capacity of stego data is low. To solve these problems, this method embed more than one bit in inaudible range, so this method can improve the capacity of the hidden message in cover data. The embedding bit position is determined by using a pseudo random number generator which has seed with remaining message length, so it is hard to detect the stego data produced by the proposed method. This proposed model is able to use not only to communicate wave file with hidden message in VoIP environment but also to hide vary information which is user basic information, authentication system, etc.

• Review of KIISC
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• v.3 no.1
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• pp.26-30
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• 1993

본 논문에서는Akl-Meijer가 설계한 랜덤 치환 발생기를 일반화한 알고리즘을 제안한다. Akl과 Meijer는 사이즈가 m인 치환(Permutation)과 0과 m!-1사이의 정수를 일대일 대응시키는 Knuth의 알고리즘을 이용하여, 선형 합동법 Y=X+C mod m! (C는 상수)에서 발생되는 난수와 일대일 대응되는 치환을 발생하는 치환 발생 알고리즘을 설계하였으며, 이를 응용하여, 이진 난수 발생기를 제시하였다. 본 논문에서는 선형 합동법 Y=AX+C mod m!(A, C는 상수)에서 발생되는 난수와 일대일 대응되는 치환 계산과정을 상삼각 행렬(Upper triangular matrix) 의 곱으로 변환하여 고속으로 계산하는 알고리즘을 제시한후, 이 알고리즘의 출력 치환을 n 개 결합하여 치환을 발생하는 랜덤치환 발생기를 설계한다. 또한 이의 암호적인 응용으로, 치환 발생기를 이용한 이진 난수 발생기를 제시한다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.4
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• pp.311-317
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• 2011

Recently, RFID is substituted for bar codes according to advance in the ubiquitous computing environments, but the RFID system has several problems such as security and privacy because it uses radio frequencies. Firstly, unauthorized reader can easily read the ID information of any Tag. Secondly, Attacker can easily fake the legitimate reader using the collected Tag ID information,such as the any legitimate tag. This paper proposed improved RFID authentication protocol based on SSG. SSG is organized only one LFSR and selection logic. Thus SSG is suitable for implementation of hardware logic in system with extremely limited resources such as RFID tag and it has resistance to known various attacks because of output bit stream for the use as pseudorandom generator. The proposed protocol is secure and effective because it is based on SSG.

• The Journal of the Korea Contents Association
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• v.8 no.4
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• pp.86-91
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• 2008

To present the design procedure of discretized 8-bit tent map executing the transformation of tent function which is one of the chaotic functions, first, the truth table of discretized tent map was written, and then according to the simplified Boolean algebra equations obtained from the truth table, the discretized map is implemented with the exclusive logic gate as a real hardware. The discretized tent map circuit which provides the feedback circuit for generating the period-8 states relevant to the 8-bit finite precision is also designed and presented in this paper. Furthermore, it might be used stream cipher system with a new key-stream circuit for generate of chaotic binary sequence.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.4
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• pp.206-211
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• 2005

We describe the design for a correlator and an access code generator in bluetooth system. These are used for a connection setting, a packet decision and a clock synchronization between Bluetooth units. The correlator consists of two blocks; carry save adder based on Wallace tree and threshold-value decision block. It determines on an useful packet and clock-synchronization for input signal of 1.0Mbps through the sliding-window correlating. The access-code generator also consists of two blocks; BCH(Bose-Chadhuri-Hocquenghem) cyclic encoder and control block. It generates the access-codes according to four steps' generation process based on Bluetooth standard. In order to solve synchronization problem, we make use of any memory as a pseudo random sequence. The proposed correlator and access-code generator were coded with VHDL. An FPGA Implementation of these modules and the simulation results are proved by Xilinx chip. The critical delay and correlative margin based on synthesis show the 4.689ns and the allowable correlation-error up to 7-bit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.110-116
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• 2016

This paper describes 1.2-V 5-Gb/s scalable low voltage signaling(SLVS) differential transmitter(TX) with a digital impedance calibration and equalizer. The proposed transmitter consists of a phase-locked loop(PLL) with 4-phase output clock, a 4-to-1 serializer, a regulator, an output driver, and an equalizer driver for improvement of the signal integrity. A pseudo random bit sequence generator is implemented for a built-in self-test. The proposed SLVS transmitter provides the output differential swing level from 80mV to 500mV. The proposed SLVS transmitter is implemented by using a 65-nm CMOS with a 1.2-V supply. The measured peak-to-peak time jitter of the implemented SLVS TX is about 46.67 ps at the data rate of 5Gb/s. Its power consumption is 1.88 mW/Gb/s.

• Proceedings of the Korea Contents Association Conference
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• 2004.11a
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• pp.344-347
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• 2004

Critical cryptography applications require the production of an unpredictable and unbiased stream of binary data derived from a fundamental noise mechanism. In this paper, we proposed a RNG with Gaussian noise using filter algorithm. The proposed scheme is designed to reduce the statistical property of the biased bit stream in the output of a RNG. Experimental show that we analysis the loss rate according to window size and propose optimum window size.

• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.319-322
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• 2002

In this paper, we present a digital authentication technique using content-based watermarking in digital images. To digest the image contents, Hopfield network is employed on the block-based edge image. The Hopfield function extracts the same tit fur similarly looking blocks so that the values are unlikely to change to the innocuous manipulations while being changed far malicious manipulations. By inputting the extracted bit sequence with secret key to the cryptographic hash function, we generate a watermark for each block by seeding a pseudo random number generator with a hash output Therefore, the proposed authentication technique can distinguish between malicious attacks and innocuous attacks. Watermark embedding is based on the block-based spread spectrum method in DCT domain and the strength of watermark is adjusted according to the local statistics of DCT coefficients in a zig-zag scan line in AC subband. The numerical experiments show that the proposed technique is very efficient in the performance of robust authentication.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.4
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• pp.123-134
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• 2004

In this paper a high speed architecture of the RC4 stream cipher is proposed and its FPGA implementation is presented. Compared to the conventional RC4 designs which have long initialization operation or use double or triple S-arrays to reduce latency delay due to S-array initialization phase, the proposed architecture for RC4 stream cipher eliminates the S-array initialization operation using 256-bit valid entry scheme and supports 40/128-bit key lengths with efficient modular arithmetic hardware. The proposed RC4 stream cipher is implemented using Xilinx XCV1000E-6H240C FPGA device. The designed RC4 stream cipher has about a throughput of 106 Mbits/sec at 40 MHz clock and thus can be applicable to WEP processor and RC4 key search processor.