• 대한교통학회지
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• 제20권2호
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• pp.149-159
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• 2002

다이아몬드 인터체인지에서 사용되는 두 가지 유형의 3현시 신호 체계의 운영결과를 다양한 교통상황 하에서 분석하였다. 본 연구를 수행하기 위하여 Hardware-in-the-loop 장치를 CORSIM 프로그램과 연결하여 사용하였으며, 운영결과는 평균지체와 총 정지수의 두 가지 효과척도를 사용하여 평가하였다. 평가결과 두 가지 3현시 신호 체계는 평균적으로 평균지체에 관해서는 동일한 결과를 나타내었으나 총 정지수는 다른 결과를 나타내었다. 또한 평균지체는 교통패턴과 인터체인지 거리에 따라 큰 영향을 받는 것으로 파악되었다. 총 정지수는 인터체인지 거리가 증가함에 따라 감소되었고, 두 가지 3현시 신호체계의 운영효과를 비교 평가할 수 있는 척도로 평가되었다. 그리고 Hardware-in-the-loop 장치를 결합하여 현재 시뮬레이션 기술의 적용영역을 확장할 수 있음을 구현하여 예시하였다.

• 한국전기전자재료학회논문지
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• 제21권12호
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• pp.1083-1089
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• 2008

We studied the dielectric characteristics of low-k SiOCH thin films by Ellipsometry. The SiOCH thin films were prepared by deposition of BTMSM precursors on p-Si wafer by CCP-PECVD method. The nano-porous structural organic/inorganic hybrid-type of SiOCH thin films correlated directly to the formation of low dielectrics close to pore(k=1). The structural groups including highly dense pores in SiOCH thin films originated the anisotropic geometry type of network structure directing to complex refractive characteristics of SiOCH single layer on the p-Si wafer. The linearly polarized beam of Xe-ramp in the range from 190 nm to 2100 nm introduced to the surface of SiOCH thin film, and the reflected beam was Elliptically polarized by complex refractive coefficients of SiOCH dipole groups. The amplitude variation $\Psi$ and phase variation $\Delta$ of the relative reflective coefficients between perpendicular and parallel components to the incident plane were measured by Ellipsometry. The complex optical constants n and k as well as the dielectric constant and thickness of SiOCH thin films were driven by the measured value of $\Psi$ and $\Delta$.

• Journal of Electrical Engineering and Technology
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• 제10권5호
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• pp.1989-2000
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• 2015

In this paper, digital peak current mode control for single phase H-bridge inverters is developed and implemented. The digital peak current mode control is achieved by directly controlling the PWM signals by cycle-by-cycle current limitation. Unlike the DC-DC converter where the output voltage always remains in the positive region, the output of DC-AC inverter flips from positive to negative region continuously. Therefore, when the inverter operates in negative region, the control should be changed to valley current mode control. Thus, a novel control logic circuit is required for the function and need to be analyzed for the hardware to track the sinusoidal reference in both regions. The problem of sub-harmonic instability which is inherent with peak current mode control is also addressed, and then proposes the digital slope compensation in constant-sloped external ramp to suppress the oscillation. For unipolar PWM switching method, an adaptive slope compensation in digital manner is also proposed. In this paper, the operating principles and design guidelines of the proposed scheme are presented, along with the performance analysis and numerical simulation. Also, a 200W inverter hardware prototype has been implemented for experimental verification of the proposed controller scheme.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 추계학술대회 논문집 학회본부
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• pp.147-150
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• 1988

Since the integration level of VLSI circuits progresses very quickly, a highly reliable thin $SiO_2$ film is required to fabricate a small-geometry MOS device. In the present study we have attempted to eliminate the failure-causing defects that develop in thin oxide films during the oxidation step by performing a long-time preoxidation and postoxidation annealing. The TDDB test and the copper decoration method were used to calculate the oxide defects density of MOS device. The dielectric reliability of high-quality thin oxides have been studied by using the time-zero-dielectric-breakdown (ramp-voltage-stressed I-V) and time-dependent-dielectric -breakdown (Constant-stressed I-V) tests. Failure times against temperature and electric field are examined and acceleration factors are abtained for each parameter. Based on the data obtained, breakdown wearout limitation for thin oxide films is estimated.

• Transactions on Electrical and Electronic Materials
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• 제8권5호
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• pp.215-217
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• 2007

Recently, color reproduction properties have attracted lots of attention with mass production of LCD especially corresponding to TV application and achievement of color reproduction properties such as CRT have been considered one of technical goals for high quality display. However, revision of the color reproduction properties only with CF(color filter) have fundamental limitations and resultant decrease in the transmittance of panel causes demand on high brightness of BL(Back Light). In this paper, we present such a method in which by optimization of original light spectrum from the BL source will improves the color reproduction properties corresponding to them of the CRT. When the intensity of RED and Green-Blue from ramp is revised densely, the characteristics different from CCFL(Cold Cathode Fluorescent Lamp) used before become added so that about 11 % of the color reproduction properties is improved compare to the existing LCD panel.

• 전기학회논문지
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• 제56권12호
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• pp.2189-2195
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• 2007

In this paper, we propose a newly developed selective reset waveform of a ac PDP using the wide erase pulse technique with the control of address bias voltage. Although it is generally understood that the wide pulse erasing methode shows the narrow driving margin in an opposite discharge type ac PDP, we could obtain a moderate driving margin in a 3-electrode surface discharge type ac PDP. The obtained driving margin shows a strong dependency on the sustain voltage and the address bias voltage. The lower the sustain and the address bias voltage, the wider the driving margin. The pulse width of the proposed waveform is only $10{\mu}s$, which gives additional time to the sustain period, hence increases the brightness. The brightness and contrast ratio increase about 20% together comparing to the conventional ramp type selective reset waveform with the driving scheme of 10 subfield ADS method. The driving margin was measured with the line by line addressed pattern on the white test panel of 2inch diagonal size and the discharge gas was Ne+Xe4%, 400torr.

• 한국추진공학회지
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• 제8권4호
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• pp.76-83
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• 2004

CRW Tyre UAV 추진시스템은 수직으로 이착륙이 가능하고 고정익으로 고속 전진 비행이 가능한 개념으로 설계되었다. 이를 위해 추진시스템은 이착륙 시에는 로터를 구동시켜 수직으로 비행하고 고속 비행 시에는 로터를 정지시켜 날개로 사용하고 가스발생기에서 생성된 가스를 주 노즐로 분사하여 본래의 제트엔진으로 사용한다. ICV방법과 SIMULINK를 이용하여 천이 성능 해석을 수행하였다. 연료유량은 터빈 입구온도의 스텝과 과온 현상을 피하기 위해 램프 증가를 하였고 이에 따른 추력의 변화와 터빈 입구온도의 변화를 살펴보았다.

• 한국추진공학회지
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• 제6권2호
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• pp.65-74
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• 2002

전압력 회복율을 최대로 하기 위한 IRR형 램젯 공기 흡입구 초음속 확산부의 최적형상 설계를 수행하였다. 질량유량을 제약조건으로 고려하고 외부램프에서의 두 번째 경사충격파와 카울립 형상, 그리고 흡입구 목의 단면적을 설계변수로 선택하였다. 효율적인 최적화를 위해 설계변수 변환을 통한 개선된 반응면 기법을 사용하였으며 설계반복을 통해 높은 신뢰도의 반응면을 구성할 수 있었다. 최적화 기법으로 유전자 알고리즘을 사용하였으며, 이차원 Euler Code를 사용하여 공력해석을 수행하였다. 배압조건의 적용을 위해 흡입구 목 뒤로 가상의 노즐을 장착하였고 총 20회의 계산으로 종말충격파 이후의 전압력 회복율이 기준형상에 비하여 14% 향상된 초음속 확산부 최적형상을 설계할 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 춘계합동학술대회 논문집
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• pp.149-152
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• 2002

If the ambient temperature rises for AC PDP, some of the discharge cells are turned off because of the misfiring during address period. Particularly, the misfiring of the 'last scan line is more serious than that of the first. In order to compensate the misfiring in such that case, different addressing voltage is applied at each cell such as progressively increasing pulse voltage instead of constant one. As a result, the addressing time and discharge charge of the last scan line have become similar to those of the first scan line and the phenomenon of misfiring has disappeared.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1265-1267
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• 1993

The switching and the retention characteristics with the injection conditions(pulse height and pulse width) were investigated in the nonvolatile MNOS memories with thin oxide layer of $23{\AA}$ thick. The shift of flatband voltage was measured using the fast ramp C-V method and experimental results were analized using the previously developed models. It was shown that the experimental results were described quit well by the trap-assisted and modified Fowler-Nordheim tunneling models for the voltage pulse of $15V{\sim}19V,\;24V{\sim}25V$, respectively. However, the direct tunneling model was agreement with experimental values in all range of pulse height. As increasing the initial shift of the flatband voltage, the decay rate was increased. But for the same initial shift of the flatband voltage, the decay rate was smaller for low and long pulse than for high and short one.