• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.102-107
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• 2007

This paper proposes a H.264/AVC entropy decoder without embedded processor nor memory fabrication process. Many researches on H.264/AVC entropy decoders require ROM or RAM fabrication process, which is difficult to be implemented in general digital logic fabrication process. Furthermore, many researches require embedded processors for bitstream manipulation, which increases area and power consumption. This papers proposes hardwired H.264/AVC entropy decoder without embedded processor, which improves data processing speed and reduces power consumption. Furthermore, its CAVLC decoder optimizes lookup table and internal buffer without embedded memory, which reduces hardware size and can be implemented in general digital logic fabrication process without ROM or RAM fabrication process. Designed entropy decoder was embedded in H.264/AVC video decoder, and it was verified to operate correctly in the system. Synthesized in TSMC 90nm fabrication process, its maximum operation frequency is 125MHz. It supports QCIF, CIF, and QVGA image format. Under slight modification of nC register and other blocks, it also support VGA image format.

• Journal of Korea Multimedia Society
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• v.13 no.2
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• pp.216-224
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• 2010

A RAM-based Neural Network(RNN) has the advantages of processing speed and hardware implementation. In spite of these advantages, it has a saturation problem, weakness of repeated learning and extract of a generalized pattern. To resolve these problems of RNN, the 3DNS model using cumulative multi discriminator was proposed. But that model does not solve the saturation problem yet. In this paper, we proposed a adaptive weight cumulative neural net(AWCNN) using the adaptive weight neuron (AWN) for solving the saturation problem. The proposed nets improved a recognition rate and the saturation problem of 3DNS. We experimented with the MNIST database of NIST without preprocessing. As a result of experimentations, the AWCNN was 1.5% higher than 3DNS in a recognition rate when all input patterns were used. The recognition rate using generalized patterns was similar to that using all input patterns.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.396-396
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• 2013

The resistive random access memory (ReRAM) has several advantages to apply next generation non-volatile memory device, because of fast switching time, long retentions, and large memory windows. The high mobility of monolayered graphene showed several possibilities for scale down and electrical property enhancement of memory device. In this study, the monolayered graphene grown by chemical vapor deposition was transferred to $SiO_2$ (100 nm)/Si substrate and glass by using PMMA coating method. For formation of metal-oxide nanoparticles, we used a chemical reaction between metal films and polyamic acid layer. The 50-nm thick BPDA-PDA polyamic acid layer was coated on the graphene layer. Through soft baking at $125^{\circ}C$ or 30 min, solvent in polyimide layer was removed. Then, 5-nm-thick indium layer was deposited by using thermal evaporator at room temperature. And then, the second polyimide layer was coated on the indium thin film. After remove solvent and open bottom graphene layer, the samples were annealed at $400^{\circ}C$ or 1 hr by using furnace in $N_2$ ambient. The average diameter and density of nanoparticle were depending on annealing temperature and times. During annealing process, the metal and oxygen ions combined to create $In_2O_3$ nanoparticle in the polyimide layer. The electrical properties of $In_2O_3$ nanoparticle ReRAM such as current-voltage curve, operation speed and retention discussed for applictions of transparent and flexible hybrid ReRAM device.

• 유체기계공업학회:학술대회논문집
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• 2006.08a
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• pp.305-308
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• 2006

For controlling micro-flows inside a LOC (lab-on-a-chip) a syringe pump or an electronic device for EOF(electro-osmotic flow) have been used in general. However, these devices are so large and heavy that they are burdensome in the development of a portable micro-TAS (total analysis system). In this study, a new flow control system employing pressure chambers, digital switches and speed controllers was developed. This system could effectively control the micro-scale flows inside a LOC without any mechanical actuators or electronic devices We also checked the feasibility of this new control system by applying it to a LOC of micro-mixer type. Performance tests show that the developed control system has very good performance. Because the flow rate in LOC is controlled easily by throttling the speed controller, the flows in complicate microchannels network can be also controlled precisely.

• Journal of Internet Computing and Services
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• v.22 no.5
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• pp.57-67
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• 2021

Modern cloud computing is rapidly changing from traditional hypervisor-based virtual machines to container-based cloud-native environments. Due to limitations in I/O performance required for both virtual machines and containers, the use of high-speed storage (SSD, NVMe, etc.) is increasing, and in-memory computing using main memory is also emerging. Running a virtual environment on main memory gives better performance compared to other storage arrays. However, RAM used as main memory is expensive and due to its volatile characteristics, data is lost when the system goes down. Therefore, additional work is required to run the virtual environment in main memory. In this paper, we propose a hybrid in-memory storage that combines a block storage such as a high-speed SSD with main memory to safely operate virtual machines and containers on main memory. In addition, the proposed storage showed 6 times faster write speed and 42 times faster read operation compared to regular disks for virtual machines, and showed the average 12% improvement of container's performance tests.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.12
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• pp.1202-1209
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• 2004

This paper presents a design methodology of a Digital Servo Signal Processor for high speed CD-RW drive systems. The proposed Digital Servo Signal Processor enables us to develop CD-related systems for the very high speed applications and is one of the key components of the CD-RW systems. The proposed center compensation servo control is newly built for an actuator shaking due to the fast response of a step motor when it jumps to a long distance. A control method compensating for eccentricity of a disc is implemented for operating robustly at a higher rotational speed. This servo mechanism is more size efficient and less power consumed because it is implemented using a ARM7 embedded processor and hardware digital filters. Furthermore, it is convenient to upgrade firmware for the future required functions. From experimental results, we can see that the performance of the control system is improved greatly. The proposed servo algorithm shows a shorter setting time including a pull-in time and a faster access time. It can be applied easily to the DVD-ROM and the DVD-RAM which have the same optical structure.

• Journal of Power System Engineering
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• v.10 no.1
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• pp.12-18
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• 2006

A three-degree of freedom model of intake system was contrived and investigated in various ways for the purpose of the amelioration of the volumetric efficiency in a low and transient engine speed for a multi cylinder diesel engine. The basic concept beyond this model started from the theory that each degree of freedom model has volumetric efficiency peak as many as its number of the degree of freedom. The volumetric efficiency affects significantly to the engine performance; torque characteristics, fuel economy and emission level. For commercial vehicles and stationary engines, the engine is designed so as to produce their best performance near the normal engine speeds, thus the low engine speed area has a tendency of poor volumetric efficiency. The aim of this study was highlighted on the amelioration of volumetric efficiency of low engine speed area in a multi cylinder diesel engine matched with an additional Helmholtz resonator. By the use of VIS(variable induction system) volumetric efficiency at low engine speed range was significantly improved. The availability of control by combination of VIS and CIS(conventional induction system) will be proposed as a variable induction system that would be an appropriate model for amelioration of the volumetric efficiency at low engine speed.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.345-348
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• 2000

In this paper, We described the procedures to generate an input-output buffer information specification (IBIS) model in digital IC circuits. We gives the method to describe IBIS standard I/O for the characteristics of I/O buffer and to represent its electrical characteristics. The parameters of I/O structure for I/O buffer modelling are also referred, and an IBIS model for CMOS, TTL IC, ROM and RAM constructed amounts about 216. This IBIS model can be used to the simulation of signal integrity of high speed circuits in a PCB level.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.381-384
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• 2001

This paper describes the features and development of a RAM compiler that can generate low power, high speed, synchronous CMOS SRAM. The compiled SRAM can be configurable from 64bytes to 16Kbytes in one bank and has 2ns access time typically. Basic cells are developed using 2-poly, 4-metal 0.35um CMOS technology. This SRAM compiler is developed using SKIL $L^{TM}$ language and generates layout and schematic in Cadence environment.

• 한국컴퓨터산업교육학회:학술대회논문집
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• 2003.11a
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• pp.75-78
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• 2003

An ideal semiconductor memory technology would combine or unify the attractive features of these technologies without acquiring any of the unattractive features. Such a memory technology, Phase Change RAM is now being developed using the class of elements known as chalcogenides. It is expected that this technology will eventually allow chips that have SRAM speed, DRAM cost, and Flash power characteristics and non-volatility.