• 대한전자공학회논문지SD
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• 제44권12호
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• pp.102-107
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• 2007

본 논문에서는 메모리 공정이 필요 없고 내장 프로세서를 사용하지 않는 H.264/AVC 엔트로피 복호기를 제안한다. 기존에 발표된 H.264/AVC 엔트로피 복호기의 경우 상당수의 연구가 내부의 ROM 또는 RAM이 필요하기 때문에 일반적인 디지털 로직 공정에서 구현이 어렵다. 또한 상당수의 연구가 비트열 처리를 위하여 내장 프로세서를 사용하기 때문에 면적이 크고 전력소모가 많은 단점을 가지고 있다. 본 논문에서는 내장 프로세서를 사용하지 않는 H.264/AVC Hardwired 엔트로피 복호기를 제안함으로써 데이터 처리 속도를 증가시키고 전력 소모를 줄인다. 또한 CAVLC 복호기에서 복호 시에 이용되는 룩업 테이블 및 저장 공간을 최적화하고 내장 메모리를 사용하지 않는 구조를 제안함으로써, 기존 연구에 비해 하드웨어 크기를 줄이고 ROM 또는 RAM이 지원되지 않는 디지털 로직 제조 공정에서도 쉽게 구현이 가능하다. 설계된 엔트로피 복호기는 H.264/AVC 비디오 복호기의 일부로 내장되어 전체 시스템에서 동작하는 것을 검증하였다. TSMC 90nm 공정으로 합성한 결과 최대동작주파수는 125MHz이며, QCIF, CIF, QVGA 영상을 지원할 뿐만 아니라 nC 레지스터 등 약간의 수정을 통해서 VGA 영상도 지원이 가능하다.

• 한국멀티미디어학회논문지
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• 제13권2호
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• pp.216-224
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• 2010

RAM 기반 신경망은 빠른 처리 속도와 하드웨어 구현의 용이성 등의 장점을 가지고 있지만 반면에 메모리의 포화 문제, 반복학습, 일반화 패턴 추출의 어려움 등의 단점도 가지고 있다. 이런 단점을 극복하기 위해 누적 다중 판별자를 가지는 3차원 뉴로 시스템(3DNS) 등이 제안되었지만 메모리 포화 문제는 해결하지는 못하였다. 본 논문에서는 메모리 포화 문제를 해결하기 위하여 적응적 가중치를 가지는 AWN (Adaptive Weight Neuron)을 사용한 적응적 가중치 누적 신경망(AWCNN)을 제안한다. 제안된 모델은 AWN으로 3DNS을 개선하여 인식률과 메모리 포화 문제 해결을 향상하였다. 제안된 시스템의 평가는 전처리 과정 없이 NIST의 MNIST에서 제공하는 자료를 이용하여 실험하였다. AWCNN은 3DNS보다 1.5%이상의 향상된 인식률을 보였고 일반화 패턴을 이용한 인식에서는 모든 입력 패턴의 교육된 것과 비슷한 성능을 얻었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.396-396
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• 2013

The resistive random access memory (ReRAM) has several advantages to apply next generation non-volatile memory device, because of fast switching time, long retentions, and large memory windows. The high mobility of monolayered graphene showed several possibilities for scale down and electrical property enhancement of memory device. In this study, the monolayered graphene grown by chemical vapor deposition was transferred to $SiO_2$ (100 nm)/Si substrate and glass by using PMMA coating method. For formation of metal-oxide nanoparticles, we used a chemical reaction between metal films and polyamic acid layer. The 50-nm thick BPDA-PDA polyamic acid layer was coated on the graphene layer. Through soft baking at $125^{\circ}C$ or 30 min, solvent in polyimide layer was removed. Then, 5-nm-thick indium layer was deposited by using thermal evaporator at room temperature. And then, the second polyimide layer was coated on the indium thin film. After remove solvent and open bottom graphene layer, the samples were annealed at $400^{\circ}C$ or 1 hr by using furnace in $N_2$ ambient. The average diameter and density of nanoparticle were depending on annealing temperature and times. During annealing process, the metal and oxygen ions combined to create $In_2O_3$ nanoparticle in the polyimide layer. The electrical properties of $In_2O_3$ nanoparticle ReRAM such as current-voltage curve, operation speed and retention discussed for applictions of transparent and flexible hybrid ReRAM device.

• 유체기계공업학회:학술대회논문집
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• 유체기계공업학회 2006년 제4회 한국유체공학학술대회 논문집
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• pp.305-308
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• 2006

For controlling micro-flows inside a LOC (lab-on-a-chip) a syringe pump or an electronic device for EOF(electro-osmotic flow) have been used in general. However, these devices are so large and heavy that they are burdensome in the development of a portable micro-TAS (total analysis system). In this study, a new flow control system employing pressure chambers, digital switches and speed controllers was developed. This system could effectively control the micro-scale flows inside a LOC without any mechanical actuators or electronic devices We also checked the feasibility of this new control system by applying it to a LOC of micro-mixer type. Performance tests show that the developed control system has very good performance. Because the flow rate in LOC is controlled easily by throttling the speed controller, the flows in complicate microchannels network can be also controlled precisely.

• 인터넷정보학회논문지
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• 제22권5호
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• pp.57-67
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• 2021

Modern cloud computing is rapidly changing from traditional hypervisor-based virtual machines to container-based cloud-native environments. Due to limitations in I/O performance required for both virtual machines and containers, the use of high-speed storage (SSD, NVMe, etc.) is increasing, and in-memory computing using main memory is also emerging. Running a virtual environment on main memory gives better performance compared to other storage arrays. However, RAM used as main memory is expensive and due to its volatile characteristics, data is lost when the system goes down. Therefore, additional work is required to run the virtual environment in main memory. In this paper, we propose a hybrid in-memory storage that combines a block storage such as a high-speed SSD with main memory to safely operate virtual machines and containers on main memory. In addition, the proposed storage showed 6 times faster write speed and 42 times faster read operation compared to regular disks for virtual machines, and showed the average 12% improvement of container's performance tests.

• 제어로봇시스템학회논문지
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• 제10권12호
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• pp.1202-1209
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• 2004

This paper presents a design methodology of a Digital Servo Signal Processor for high speed CD-RW drive systems. The proposed Digital Servo Signal Processor enables us to develop CD-related systems for the very high speed applications and is one of the key components of the CD-RW systems. The proposed center compensation servo control is newly built for an actuator shaking due to the fast response of a step motor when it jumps to a long distance. A control method compensating for eccentricity of a disc is implemented for operating robustly at a higher rotational speed. This servo mechanism is more size efficient and less power consumed because it is implemented using a ARM7 embedded processor and hardware digital filters. Furthermore, it is convenient to upgrade firmware for the future required functions. From experimental results, we can see that the performance of the control system is improved greatly. The proposed servo algorithm shows a shorter setting time including a pull-in time and a faster access time. It can be applied easily to the DVD-ROM and the DVD-RAM which have the same optical structure.

• 동력기계공학회지
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• 제10권1호
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• pp.12-18
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• 2006

A three-degree of freedom model of intake system was contrived and investigated in various ways for the purpose of the amelioration of the volumetric efficiency in a low and transient engine speed for a multi cylinder diesel engine. The basic concept beyond this model started from the theory that each degree of freedom model has volumetric efficiency peak as many as its number of the degree of freedom. The volumetric efficiency affects significantly to the engine performance; torque characteristics, fuel economy and emission level. For commercial vehicles and stationary engines, the engine is designed so as to produce their best performance near the normal engine speeds, thus the low engine speed area has a tendency of poor volumetric efficiency. The aim of this study was highlighted on the amelioration of volumetric efficiency of low engine speed area in a multi cylinder diesel engine matched with an additional Helmholtz resonator. By the use of VIS(variable induction system) volumetric efficiency at low engine speed range was significantly improved. The availability of control by combination of VIS and CIS(conventional induction system) will be proposed as a variable induction system that would be an appropriate model for amelioration of the volumetric efficiency at low engine speed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.345-348
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• 2000

In this paper, We described the procedures to generate an input-output buffer information specification (IBIS) model in digital IC circuits. We gives the method to describe IBIS standard I/O for the characteristics of I/O buffer and to represent its electrical characteristics. The parameters of I/O structure for I/O buffer modelling are also referred, and an IBIS model for CMOS, TTL IC, ROM and RAM constructed amounts about 216. This IBIS model can be used to the simulation of signal integrity of high speed circuits in a PCB level.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.381-384
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• 2001

This paper describes the features and development of a RAM compiler that can generate low power, high speed, synchronous CMOS SRAM. The compiled SRAM can be configurable from 64bytes to 16Kbytes in one bank and has 2ns access time typically. Basic cells are developed using 2-poly, 4-metal 0.35um CMOS technology. This SRAM compiler is developed using SKIL $L^{TM}$ language and generates layout and schematic in Cadence environment.

• 한국컴퓨터산업교육학회:학술대회논문집
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• 한국컴퓨터산업교육학회 2003년도 제4회 종합학술대회 논문집
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• pp.75-78
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• 2003

An ideal semiconductor memory technology would combine or unify the attractive features of these technologies without acquiring any of the unattractive features. Such a memory technology, Phase Change RAM is now being developed using the class of elements known as chalcogenides. It is expected that this technology will eventually allow chips that have SRAM speed, DRAM cost, and Flash power characteristics and non-volatility.