• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2006.05a
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• pp.21-40
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• 2006

[ ${\Box}$ ] Opportunities for PRAM Nearly ideal memory characteristics Potential for high density & low cost memory ${\Box}$ Technical Challenges Writing current reduction is the most urgent issue. ${\to}$ chalcogenide, programming volume, current density, heat loss control Improvement of writing speed, reliability ${\Box}$ Prospects (PRAM as a Mainstream Memory) Evenn, We have demonstrated 256Mb PRAM Realization of high density and low cost PRAM with good reliability will be key succss factor. We need to develop PRAM specific applications.

• 한국신재생에너지학회:학술대회논문집
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• 2009.11a
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• pp.431-434
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• 2009

Conceptual study of an open-circuit type low-speed wind tunnel for test of wind turbine blade is conducted. The tunnel is constituted of a settling chamber, a contraction, closed and open test sections, a diffuser, two corners, a cross leg and a fan and motor. For the performance test, the closed test section width of 1.8 m, height of 1.8 m and length of 5.25 m is selected. The open test section with dimension width of 1.8 m, height of 1.8 m and length of 4.14 m is adopted for aeroacoustic test. The contraction ratio is 9 to 1 and maximum speed in the closed test section is 67 m/sec. Input power in the tunnel is about 238 kW and its energy ratio is 3.6. The wind tunnel designed in present study will be an effective tool in research and development of wind turbine.

• Journal of KIISE:Information Networking
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• v.32 no.4
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• pp.471-482
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• 2005

The high-speed network permits Grid computing to handle large problem of management areas and share various computational resources. As there are many resources and changes of them in Grid computing, the resources should be detected effectively and matched correctly with tasks to provide high performance. In this paper, we propose a mechanism that maximizes the performance of Grid computing systems. According to a priority, grade and site of heterogeneous resources, we assign tasks to those resources. Initially, a volunteer's priority and ranking are determined by static information like as CPU speed, RAM size, storage size and network bandwidth. And then, the rank of resources is decided by considering dynamic information such as correctness, response time, and error rate. We find that overall Grid system performance is improved and high correctness using resource reallocation mechanism is achieved.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.5
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• pp.205-211
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• 2009

The Weightless Neural Network(WNN) has the advantage of the processing speed, less computability than weighted neural network which readjusts the weight. Especially, The behavior information such as sequential gesture has many serial correlation. So, It is required the high computability and processing time to recognize. To solve these problem, Many algorithms used that added preprocessing and hardware interface device to reduce the computability and speed. In this paper, we proposed the Ram based Sequential Cumulative Neural Network(SCNN) model which is sign language recognition system without preprocessing and hardware interface. We experimented with using compound words in continuous korean sign language which was input binary image with edge detection from camera. The recognition system of sign language without preprocessing got 93% recognition rate.

• Journal of Korea Multimedia Society
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• v.10 no.8
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• pp.1029-1038
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• 2007

A smart card based on the existing Java card platform executes and installs an application only when the power is supplied for a minute. And preparing for unexpected power outrage, the execution state of an application and all the data that are modified during execution are saved in the heap. This kind of frequent data update of an EEPROM data is a main cause of reducing the life-cycle of a smart card. This is because the smart card has been developed not considering the current situation that the power is always supplied, and by this time it has continuously kept its old architecture. This paper explains the high performance Java card system free power restriction. The system improves not only application saving mechanism, but memory architecture. In special, we deploy RAM for running an applet, as well as EEPROM for downloading an application. Through proposed mechanism, we can find out performance evaluation that the creation speed of an applet and the execution speed of a method increase up to 58% and 33% respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.28-35
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• 2007

In this paper, an ultra low voltage SRAM design method based on dual-boosted cell bias technique is described. For each read/write cycle, the wordline and cell power node of the selected SRAM cells are boosted into two different voltage levels. This enhances SNM(Static Noise Margin) to a sufficient amount without an increase of the cell size, even at sub 1-V supply voltage. It also improves the SRAM circuit speed owing to increase of the cell read-out current. The proposed design technique has been demonstrated through 0.8-V, 32K-byte SRAM macro design in a $0.18-{\mu}m$ CMOS technology. Compared to the conventional cell bias technique, the simulation confirms an 135 % enhancement of the cell SNM and a 31 % faster speed at 0.8-V supply voltage. This prototype chip shows an access time of 23 ns and a power dissipation of $125\;{\mu}W/Hz$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7B
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• pp.647-659
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• 2003

LPM(Longest Prefix Matching)searching in If address lookup is a major bottleneck of IP packet processing in the high speed router. In the conventional lookup table for the LPM searching in CAM(Content Addressable Memory) the complexity of fast update take 0(1). In this paper, we designed pipeline architecture for fast update of 0(1) cycle of lookup table and high throughput and low area complexity on LPM searching. Lookup-table architecture was designed by CAM(Content Addressable Memory)away that uses 1bit RAM(Random Access Memory)cell. It has three pipeline stages. Its LPM searching rate is affected by both the number of key field blocks in stage 1 and stage 2, and distribution of matching Point. The RTL(Register Transistor Level) design is carried out using Verilog-HDL. The functional verification is thoroughly done at the gate level using 0.35${\mu}{\textrm}{m}$ CMOS SEC standard cell library.

• Journal of IKEEE
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• v.27 no.4
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• pp.494-500
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• 2023

Image processing is currently used in various fields. Among them, autonomous vehicles, medical image processing, and robot control require fast image processing response speeds. To fulfill this requirement, hardware design for real-time processing is being actively researched. In addition to the size of the input image, the hardware processing speed is affected by the size of the inactive video periods that separate lines and frames in the image. In this paper, we design three different scaler structures based on the type of line memories, which is closely related to the inactive video periods. The structures are designed in hardware using the Verilog standard language, and synthesized into logic circuits in a field programmable gate array environment using Xilinx Vivado 2023.1. The synthesized results are used for frame rate analysis while comparing standard image sizes that can be processed in real time.

• Journal of Advanced Navigation Technology
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• v.13 no.4
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• pp.509-514
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• 2009

In this paper, we designed and analyzed 256GB DRAM-based SSD storage using DDR1 memory and PCI-e interface. SSD is a storage system that uses DRAM or NAND Flash as primary storage media. Since the SSD read and write data directly to memory chips, which results in storage speeds far greater than conventional magnetic storage devices, HDD. Architecture of the proposed SSD system has performance of high speed data processing duo to use multiple RAM disks as primary storage and PCI-e interface bus as communication path of RAM disks. We constructed experimental system with UNIX, Windows/Linux server, SAN Switch, and Ethernet Switch and measured IOPS and bandwidth of proposed SSD using IOmeter. In experimental results, it has been shown that IOPS, 470,000 and bandwidth,800MB/sec of the DDR-1 SSD is better than those of the HDD and Flash-based SSD.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.4
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• pp.383-390
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• 2010

This paper describes multiparticle finite element model (MPFEM)-based powder compaction simulations performed to demonstrate the densification of compacted aluminum powders. A 2D MPFEM was used to explore the densification of a collection of aluminum particles with different average particle sizes under various ram speeds. Individual particles are discretized using a finite element mesh for a detailed description of contact mechanics. Porous aluminum powders with average particle sizes of $20\;{\mu}m$ and $3\;{\mu}m$ were compressed uniaxially at ram speeds of 5, 15, 30, and 60 mm/min by using an MTS servo-hydraulic tester. The slow ram speed was of great advantage to powder densification in low compaction force due to sufficient particle rearrangement. Owing to a decrease in the average particle size of aluminum, the compaction force increased.