• Journal of KIISE:Computer Systems and Theory
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• v.34 no.8
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• pp.327-336
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• 2007

Lots of effort toward design optimizations have been paid for a cost-effective system design in various ways from a transistor level to RTL designs. In this paper, we propose a bit level optimization of an adder design for expanding its design space. For the bit-level optimization, a heterogeneous adder organization utilizing a mixture of carry propagation schemes is proposed to design a delay-area efficient adder which were not available in an ordinary design space. Then, we develop an optimization method based on Integer Linear Programming to search the expanded design space of the heterogeneous adder. The novelty of the Proposed architecture and optimization method is introducing a bit level reconstruction/recombination of IPs which have same functionality but different speed and area characteristics for producing more find-grained delay-area optimization.

• Journal of IKEEE
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• v.24 no.3
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• pp.838-844
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• 2020

In this paper, we propose an efficient Viterbi processor using Joint Viterbi detection and decoding (JVDD) algorithm for a for bluetooth low energy (BLE) system. Since the convolutional coded Gaussian minimum-shift keying (GMSK) signal is specified in the BLE 5.0 standard, two Viterbi processors are needed for detection and decoding. However, the proposed JVDD scheme uses only one Viterbi processor by modifying the branch metric with inter-symbol interference information from GMSK modulation; therefore, the hardware complexity can be significantly reduced without performance degradation. Low-latency and low-complexity hardware architecture for the proposed JVDD algorithm was proposed, which makes Viterbi decoding completed within one clock cycle. Viterbi Processor RTL synthesis results on a GF55nm process show that the gate count is 12K and the memory unit and the initial latency is reduced by 33% compared to the modified state exchange (MSE).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.459-462
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• 2005

In this paper, we investigate the high precision location estimation algorithm in 2.45GHz band RTLS with multiple tags. The location is estimated in LOS environments, 300m ${\times}$ 300m area, and 2D coordinates adopting a TDOA scheme which is not necessitate the transmission time of tags. We evaluate the average estimation error in distance assuming that tags are randomly distributed and the readers(3${\sim}$8) are uniformly(equal space) placed in test area. In results, average estimation error is 3.12m and 1.47m at reader numbers of 4 and 8, respectively. Minimum estimation error is obtained when the accumulated receiving signal from a tag is 3 or 4 regardless of available reader numbers. The error is less than 3m, satisfies the specification of RTLS.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.9_10
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• pp.485-496
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• 2008

As the complexity of SoC (System-on-Chip) design increases dramatically. traditional system performance analysis and verification methods based on RTL (Register Transfer Level) are no more valid for increasing time-to-market pressure. Therefore a new design methodology is desperately required for system verification in early design stages. and hardware software (HW-SW) cosimulation at TLM (Transaction Level Modeling) level has been researched widely for solving this problem. However, most of HW-SW cosimulators support few restricted ion levels only, which makes it difficult to integrate HW-SW cosimulators with different ion levels. To overcome this difficulty, this paper proposes a multipurpose framework for HW SW cosimulation to provide systematic SoC design flow starting from software application design. It supports various design techniques flexibly for each design step, and various HW-SW cosimulators. Since a platform design is possible independently of ion levels and description languages, it allows us to generate simulation models with various ion levels. We verified the proposed framework to model a commercial SoC platform based on an ARM9 processor. It was also proved that this framework could be used for the performance optimization of an MJPEG example up to 44% successfully.

• 한국공간정보시스템학회:학술대회논문집
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• 2007.06a
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• pp.15-20
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• 2007

최근 항만 물류 및 자산 관리 분야에서 실시간 위치 정보를 처리하는 RTLS(Real Time Locating System)시스템이 도입되고 있다. 이러한 시스템에서 RTLS 서버는 태그를 부착한 이동 객체들의 위치 데이터 스트림을 일정 시간 동안 수집하여 애플리케이션으로 전달한다. 이 때 위치 정보는 전파 굴절 현상으로 인해 오차가 발생하며, 이동 객체에 부착된 태그는 수 초 마다 위치 정보를 보고하기 때문에 시스템의 과부하를 초래하게 된다. 본 논문에서는 표준과의 호환성을 고려하고, 요구사항을 반영한 위치 데이터 스트림 처리기를 설계 및 개발하였다. RTLS 시스템의 전파 굴절 현상으로 야기되는 비정상적인 위치 오차를 보정하기 위해 맵 매칭 기법을 도입하여 위치 데이터 스트림의 신뢰성을 제공하며, 위치 변화가 없는 객체의 위치 데이터 스트림을 빠르게 정제하는 정지 상태 제거 필터를 개발하여 질의 처리 시 부하를 줄인다. 또한 각 애플리케이션의 질의 결과에 무의미한 위치 정보를 배제하는 중요 위치 수집기를 개발하여 시스템 성능을 향상시킨다.

• Information and Communications Magazine
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• v.32 no.2
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• pp.13-23
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• 2015

Real Time Location System(RTLS)는 실시간으로 사물의 위치 정보 측위를 통해 다양한 서비스를 제공하는 시스템을 말한다. RTLS 시스템은 물류, 헬스케어, 생산 시설 등 사물인터넷(IoT, Internet of Things)과 관련된 다양한 분야에서 활용되고 있다. 최근에는 경마, 미식축구 및 발레 등 여러 스포츠 종목에 도입하고자 하는 시도가 늘고 있어 동계올림픽의 각 종목을 위한 훈련, 분석, 서비스 등에의 적용을 위한 개발을 적극적으로 검토할 필요가 있다. 통상적으로 실시간 위치 추적 시스템(RTLS)은 근거리 및 실내와 같은 제한된 공간에서의 위치 확인 및 위치 추적 시스템을 통칭하고, 이동통신망 기반의 위치기반 서비스(LBS) 처럼 사람 또는 사물의 위치를 확인하지만 주로 제한된 공간에 활용되므로 '실내위치 추적 서비스(IPS: Indoor Positioning System)'라고 불리기도 한다. 본고에서는 먼저 RTLS의 기술과 이를 스포츠에 접목하기 위한 사례를 중심으로 그 동향을 분석한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.04a
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• pp.197-200
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• 2011

최근 맞벌이 및 핵가족화 등으로 보호체계가 취약해짐에 따라 아동들을 대상으로 한 범죄가 늘고 있으며, 현재 아동범죄 처벌 강화 등 아동보호 대책들을 마련하고 있지만 예방을 위한 대책이 절실히 필요하다. 이러한 문제점을 해결하기 위하여 RTLS(Real Time Location System)를 이용하여 아동의 이동경로를 실시간으로 파악하여, 아동의 위험 상황을 인지하고 보호할 수 있는 아동보호 시스템을 개발하였다. 제안한 시스템은 보호자로 하여금 아동의 실시간 위치 정보를 확인하여 빠른 대처를 통해 아동을 범죄의 위험으로부터 조금이나마 벗어날 수 있게 해줄 것으로 기대된다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Journal of KIISE:Computing Practices and Letters
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• v.9 no.2
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• pp.166-181
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• 2003

With the rapid growth of Internet, many devices such as Web TVs, PDAs and Web phones, begin to be directly connected to the Internet. These devices need real-time operating systems (RTOS) to support complex real-time applications running on them. Development of such real-time applications called embedded internet applications, is difficult due to the lack of adequate tools, especially debuggers. In this paper we present a new tracepoint debugging tool for the Qplus-T RTOS embedded system, which facilitates the instrumentations of the real-time software applications with timing trace-points. Compared with traditional breakpoint debugger, this trace-point debugger provides the ability to dynamically collect and record application data for on-line examination and for further off-line analysis. And, the trace-points can also provide the means for assigning new values to the running application's variables, without neither halting its execution nor interfering with its natural execution flow. Our trace-point debugger provides a highly efficient method for adding numerous monitoring trace-points within a real time target application such as Qplus-T internet applications, utilizing these trace-points to monitor and to analyze the application's behavior while it is running. And also, our trace debugger is different from previous one in that we can specify and detect the timing violations using its RTL (Real-Time Logic) trace experiments.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.4
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• pp.69-74
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• 2011

In this paper, we propose a foot-and-mouth disease prevention system using the RTLS technology and $A^*$ algorithm-based optimal path search method to avoid foot-and-mouth disease areas. The main features and contributions of the proposed system are as follows. First, the proposed system is developed based on active-tag for identifying status and location information of livestock. Second, the system is newly designed based on $A^*$ algorithm for supporting optimal path search services. The performance evaluation of the proposed system is performed via simulation. The results of performance evaluation show that the proposed system can efficiently support the optimal path search services.