• Proceedings of the KIEE Conference
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• 1998.11c
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• pp.801-803
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• 1998

We investigated Pt and $RuO_2$ as a bottom electrode and PZT thin film for ferroelectric applications. XRD examination shows that a mixed phase of (111) and (200) Pt peak for the temperature ranged from RT to $200^{\circ}C$, and a preferred (111) orientation for the substrate temperature of $300^{\circ}C$. From the XRD and AFM results, we recommend the substrate temperature of $300^{\circ}C$, 80 W for the Pt bottom electrode growth. From the study of an oxygen partial pressure from 0 to 50%, we learned that only Ru metal was grown with $0{\sim}5%$, a mixed phase of Ru and $RuO_2$ for $10{\sim}40%$, pure $RuO_2$ at 50%. Having optimized the bottom electrode growth conditions, we employed two step process in PZT film capacitor: PZT film growth at the low substrate temperature of $300^{\circ}C$ and then post RTA anneal treatments. PZT films were randomly oriented on $RuO_2$ and (110) preferentially oriented on Pt electrode. Leakage current density of PZT film demonstrated two to three orders higher for $RuO_2$ bottom electrode. From C-V results we observed a dielectric constant of PZT film higher than 1200. This paper presents the optimized process conditions of the bottom electrodes and properties of PZT thin films on these electrodes.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.105-106
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• 2008

Structural, optical and electrical properties of CdS films deposited by chemical bath deposition (CBD), which are a very attractive method for low-cost and large-area solar cells, are presented. Cadmium sulfide (CdS) is II-VI semiconductor with a wide band gap of approximately 2.42 eV. CdS films have a great application potential such as solar cell, optical detector and optoelectronics device. In this paper, effects of Rapid Thermal Process (RTP) on the properties of CdS films were investigated. The CdS films were prepared on a glass by chemical bath deposition (CBD) and subsequently annealed at standard temperature $(400^{\circ}C)$ and treatment time (10 min) in various atmospheres (air, vacuum and $N_2$). The CdS films treated RTP in $N_2$ for to min were showed larger grain size and higher carrier density than the other samples.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.155.2-155.2
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• 2013

Strain-relaxed SiGe layer on Si substrate has numerous potential applications for electronic and opto- electronic devices. SiGe layer must have a high degree of strain relaxation and a low dislocation density. Conventionally, strain-relaxed SiGe on Si has been manufactured using compositionally graded buffers, in which very thick SiGe buffers of several micrometers are grown on a Si substrate with Ge composition increasing from the Si substrate to the surface. In this study, a new plasma process, i.e., the combination of PIII&D and HiPIMS, was adopted to implant Ge ions into Si wafer for direct formation of SiGe layer on Si substrate. Due to the high peak power density applied the Ge sputtering target during HiPIMS operation, a large fraction of sputtered Ge atoms is ionized. If the negative high voltage pulse applied to the sample stage in PIII&D system is synchronized with the pulsed Ge plasma, the ion implantation of Ge ions can be successfully accomplished. The PIII&D system for Ge ion implantation on Si (100) substrate was equipped with 3'-magnetron sputtering guns with Ge and Si target, which were operated with a HiPIMS pulsed-DC power supply. The sample stage with Si substrate was pulse-biased using a separate hard-tube pulser. During the implantation operation, HiPIMS pulse and substrate's negative bias pulse were synchronized at the same frequency of 50 Hz. The pulse voltage applied to the Ge sputtering target was -1200 V and the pulse width was 80 usec. While operating the Ge sputtering gun in HiPIMS mode, a pulse bias of -50 kV was applied to the Si substrate. The pulse width was 50 usec with a 30 usec delay time with respect to the HiPIMS pulse. Ge ion implantation process was performed for 30 min. to achieve approximately 20 % of Ge concentration in Si substrate. Right after Ge ion implantation, ~50 nm thick Si capping layer was deposited to prevent oxidation during subsequent RTA process at $1000^{\circ}C$ in N2 environment. The Ge-implanted Si samples were analyzed using Auger electron spectroscopy, High-resolution X-ray diffractometer, Raman spectroscopy, and Transmission electron microscopy to investigate the depth distribution, the degree of strain relaxation, and the crystalline structure, respectively. The analysis results showed that a strain-relaxed SiGe layer of ~100 nm thickness could be effectively formed on Si substrate by direct Ge ion implantation using the newly-developed PIII&D process for non-gaseous elements.

• Korean Journal of Materials Research
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• v.22 no.4
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• pp.202-206
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• 2012

$CoSi_2$ was formed through annealing of atomic layer deposition Co thin films. Co ALD was carried out using bis(N,N'-diisopropylacetamidinato) cobalt ($Co(iPr-AMD)_2$) as a precursor and $NH_3$ as a reactant; this reaction produced a highly conformal Co film with low resistivity ($50\;{\mu}{\Omega}cm$). To prevent oxygen contamination, $ex-situ$ sputtered Ti and $in-situ$ ALD Ru were used as capping layers, and the silicide formation prepared by rapid thermal annealing (RTA) was used for comparison. Ru ALD was carried out with (Dimethylcyclopendienyl)(Ethylcyclopentadienyl) Ruthenium ((DMPD)(EtCp)Ru) and $O_2$ as a precursor and reactant, respectively; the resulting material has good conformality of as much as 90% in structure of high aspect ratio. X-ray diffraction showed that $CoSi_2$ was in a poly-crystalline state and formed at over $800^{\circ}C$ of annealing temperature for both cases. To investigate the as-deposited and annealed sample with each capping layer, high resolution scanning transmission electron microscopy (STEM) was employed with electron energy loss spectroscopy (EELS). After annealing, in the case of the Ti capping layer, $CoSi_2$ about 40 nm thick was formed while the $SiO_x$ interlayer, which is the native oxide, became thinner due to oxygen scavenging property of Ti. Although Si diffusion toward the outside occurred in the Ru capping layer case, and the Ru layer was not as good as the sputtered Ti layer, in terms of the lack of scavenging oxygen, the Ru layer prepared by the ALD process, with high conformality, acted as a capping layer, resulting in the prevention of oxidation and the formation of $CoSi_2$.

• Korean Journal of Materials Research
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• v.19 no.2
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• pp.90-94
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• 2009

The development of low-k materials is essential for modern semiconductor processes to reduce the cross-talk, signal delay and capacitance between multiple layers. The effect of the $CH_4$ concentration on the formation of SiOC(-H) films and their dielectric characteristics were investigated. SiOC(-H) thin films were deposited on Si(100)/$SiO_2$/Ti/Pt substrates by plasma-enhanced chemical vapor deposition (PECVD) with $SiH_4$, $CO_2$ and $CH_4$ gas mixtures. After the deposition, the SiOC(-H) thin films were annealed in an Ar atmosphere using rapid thermal annealing (RTA) for 30min. The electrical properties of the SiOC(-H) films were then measured using an impedance analyzer. The dielectric constant decreased as the $CH_4$ concentration of low-k SiOC(-H) thin film increased. The decrease in the dielectric constant was explained in terms of the decrease of the ionic polarization due to the increase of the relative carbon content. The spectrum via Fourier transform infrared (FT-IR) spectroscopy showed a variety of bonding configurations, including Si-O-Si, H-Si-O, Si-$(CH_3)_2$, Si-$CH_3$ and $CH_x$ in the absorbance mode over the range from 650 to $4000\;cm^{-1}$. The results showed that dielectric properties with different $CH_4$ concentrations are closely related to the (Si-$CH_3$)/[(Si-$CH_3$)+(Si-O)] ratio.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.80-80
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• 2009

Recently, multiferroics have attracted much attention due to their numorous potentials. In this work, we attemped to utilize the multiferroics as an alternative material for ferroelectrics. Ferroelectric materials have been stadied to ferroelectric random access memories, however, some inevitable problems prevent it from inplementation. multiferroics shows a ferroelectricity and has low process temperature $BiFeO_3$(BFO) films have good ferroelectric properties but poor leakage characterization. Thus we tried, in this work, to adopt $HfO_2$ insulating layer for metal-ferroelectric-insulator-semiconductor(MFMIS) structure to surpress to leakage current. $BiFeO_3$(BFO) thin films were fabricared by using a sol-gel method on $HfO_2/Si$ structure. Ferroelectric BFO films on a p-type Si(100)wafer with a $HfO_2$ buffer layer have been fabricated to form a metal-ferroelectric-insulator-semiconductor (MFIS) structure. The $HfO_2$ insulator were deposited by using a sol-gel method. Then, they were carried out a rapid thermal annealing(RTA) furnace at $750\;^{\circ}C$ for 10 min in $N_2$. BFO films on the $HfO_2/Si$ structures were deposited by sol-gel method and they were crystallized rapid thermal annealing in $N_2$ atomsphere at $550\;^{\circ}C$ for 5 min. They were characterized by atomic force microscopy(AFM) and Capacitance-voltage(C-V) curve.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.7 no.2
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• pp.309-314
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• 1997

The electrical properties of thick PZT films deposited on Ag-Pd/$Al_2O_3$ and Pt electrodes were carefully investigated according to the annealing methods and the sub-strates. For electrical properties measurements, silver was deposited on PZT films as top electrode. The crystallogaphic structure of the films was examined by standard X-ray diffraction method to determine which crystalline phase was present. Dielctric constant was measured at 1 kHz, 10 mV by using a HP4284A. The electrical properties of PZT films with 3 wt% PbO addition were not improved. It was also found that the Ag-Pd layer has a good possibility as electrode instead of Pt. It seems clear from the present experiments that the thick PZT films having the good electrical properties can certainly be obtained using spin on technique combined with rapid thermal annealing.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.45-49
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• 2014

In this study, we grew non-polar ZnO nanostructure on (1-102) R-plane sapphire substrates. As for growth method of ZnO, we used hydrothermal synthesis which is known to have the advantages of low cost and easy process. For growth of non-polar, the deposited AZO seed buffer layer with of 80 nm on R-plane sapphire by radio frequency magnetron sputter was annealed by RTA(rapid thermal annealing) in the argon atmosphere. After that, we grew ZnO nanostructure on AZO seed layer by the added hexamethylenetramine (HMT) solution and sodium citrate at $90^{\circ}C$. With two types of additives into solution, we investigated the structures and shapes of ZnO nanorods. Also, we investigate the possibility of formation of 2D non-polar ZnO layer by changing the ratio of two additives. As a result, we could get the non-polar A-plane ZnO layer with well optimized additives' concentrations.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.3
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• pp.1204-1227
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• 2020

The tradeoff between energy conservation and traffic balancing is a dilemma problem in Wireless Sensor Networks (WSNs). By analyzing the intrinsic relationship between cluster properties and long distance transmission energy consumption, we characterize three node sets of the cluster as a theoretical foundation to enhance high performance of WSNs, and propose optimal solutions by introducing rendezvous and Mobile Elements (MEs) to optimize energy consumption for prolonging the lifetime of WSNs. First, we exploit an approximate method based on the transmission distance from the different node to an ME to select suboptimal Rendezvous Point (RP) on the trajectory for ME to collect data. Then, we define data transmission routing sequence and model rendezvous planning for the cluster. In order to achieve optimization of energy consumption, we specifically apply the economic theory called Diminishing Marginal Utility Rule (DMUR) and create the utility function with regard to energy to develop an adaptive energy consumption optimization framework to achieve energy efficiency for data collection. At last, Rendezvous Transmission Algorithm (RTA) is proposed to better tradeoff between energy conservation and traffic balancing. Furthermore, via collaborations among multiple MEs, we design Two-Orbit Back-Propagation Algorithm (TOBPA) which concurrently handles load imbalance phenomenon to improve the efficiency of data collection. The simulation results show that our solutions can improve energy efficiency of the whole network and reduce the energy consumption of sensor nodes, which in turn prolong the lifetime of WSNs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.12
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• pp.1001-1007
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• 2001

In this study, high dielectric materials, (Pb,La)Ti $O_3$ thin films were fabricated by PLD (Pulsed Laser Deposition) method and investigated in terms of structural and electrical characteristics in order to develope the dielectric materials for the use of new capacitor layers of Giga bit-level DRAM. The deposition conditions were examined in order to fabricate uniform thin films through systematic changes of oxygen pressures and substrate temperature. The uniform thickness and smooth morphology of (P $b_{0.72}$L $a_{0.28}$)Ti $O_3$ thin films were obtained at the conditions of substrate-target distance 5.5[cm], laser energy density 2.1[J/$\textrm{cm}^2$], oxygen pressure 200[mTorr] and substrate temperature 500[$^{\circ}C$]. After the (P $b_{0.72}$L $a_{0.28}$)Ti $O_3$ thin films were fabricated under the above conditions, they were post-annealed by RTA process in order to increase the dielectric constant. The film thickness of 1200 [$\AA$] had dielectric constant 821. Assuming that operating voltage is 2V, leakage current density of (P $b_{0.72}$L $a_{0.28}$)Ti $O_3$ thin films would result into 10$^{-7}$ [A/$\textrm{cm}^2$] and satisfied the specification of 256M DRAM planar capacitor, 4$\times$10$^{-7}$ [A/$\textrm{cm}^2$]m}^2$]